Datasheet SN74LVC138ADR, SN74LVC138APWLE, SN74LVC138APWR, SN74LVC138AD, SN74LVC138ADBR Datasheet (Texas Instruments)

SN54LVC138A, SN74LVC138A

3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS

SCAS291I – MARCH 1993 – REVISED OCTOBER 1998

D

EPIC

 (Enhanced-Performance Implanted

CMOS) Submicron Process

D

ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)

D

Latch-Up Performance Exceeds 250 mA Per
JESD 17

D

Typical V
< 0.8 V at V

D

Typical V
> 2 V at V

D

Inputs Accept Voltages to 5.5 V

D

Package Options Include Plastic

(Output Ground Bounce)

OLP

= 3.3 V, TA = 25°C

CC

(Output VOH Undershoot)

OHV

= 3.3 V, TA = 25°C

CC

Small-Outline (D), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Chip Carriers (FK) and
Flat (W) Package, and DIPs (J)

description

The SN54LVC138A 3-line to 8-line decoder/
demultiplexer is designed for 2.7-V to 3.6-V V
operation and the SN74LVC138A 3-line to 8-line

CC

SN54LVC138A...J OR W PACKAGE

SN74LVC138A. . . D, DB, OR PW PACKAGE

SN54LVC138A. . . FK PACKAGE

C

G

2A

NC

G

2B

G1

(TOP VIEW)

A

1

B

2

C

3

G2A

4

G2B

5

G1

6

Y7

7

GND

8

(TOP VIEW)

BANC

3212019

4
5
6
7
8

910111213

16
15
14
13
12
11
10

9

V

CC

V
Y0
Y1
Y2
Y3
Y4
Y5
Y6

Y0

18
17
16
15
14

CC

Y1
Y2
NC
Y3
Y4

decoder/demultiplexer is designed for 1.65-V to

Y6

3.6-V V

operation.

CC

The ’LVC138A devices are designed for high­performance memory-decoding or data-routing

Y7

GND

NC – No internal connection

NC

Y5

applications requiring very short propagation
delay times. In high-performance memory systems, these decoders minimize the effects of system decoding.
When employed with high-speed memories utilizing a fast enable circuit, the delay times of these decoders and
the enable time of the memory are usually less than the typical access time of the memory. This means that
the effective system delay introduced by the decoders is negligible.

The conditions at the binary-select inputs and the three enable inputs select one of eight output lines. Two
active-low enable inputs and one active-high enable input reduce the need for external gates or inverters when
expanding. A 24-line decoder can be implemented without external inverters and a 32-line decoder requires
only one inverter. An enable input can be used as a data input for demultiplexing applications.

Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators
in a mixed 3.3-V/5-V system environment.

The SN54L VC138A is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74LVC138A is characterized for operation from –40°C to 85°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  1998, Texas Instruments Incorporated

On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.

1

SN54LVC138A, SN74LVC138A
3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS

SCAS291I – MARCH 1993 – REVISED OCTOBER 1998

FUNCTION TABLE

ENABLE INPUTS

G1 G2A G2B C B A Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7

X H X X X X H H H H H H H H
X XHXXXHHHHHHHH
LXXXXXHHHHHHHH
HLLLLLLHHHHHHH
HLLLLHHLHHHHHH
HLLLHLHHLHHHHH
HLLLHHHHHLHHHH
HLLHLLHHHHLHHH
HLLHLHHHHHHLHH
HLLHHLHHHHHHLH
HL LHHHHHHHHHHL

SELECT INPUTS OUTPUTS

logic symbols (alternatives)

1

A

2

B

3

C

6

G1

4

G2A

5

G2B

†

These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

Pin numbers shown are for the D, DB, J, PW, and W packages.

BIN/OCT

1
2
4

&

EN

†

15

0
1
2
3
4
5
6
7

14
13
12
11
10

Y0
Y1
Y2
Y3
Y4
Y5

9

Y6

7

Y7

G1
G2A
G2B

1

A

2

B

3

C

6
4

5

DMUX

0

G

2

&

0

0

1

7

2
3
4
5
6
7

15
14
13
12
11
10

Y0
Y1
Y2
Y3
Y4
Y5

9

Y6

7

Y7

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

logic diagram (positive logic)

1

A

SN54LVC138A, SN74LVC138A

3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS

SCAS291I – MARCH 1993 – REVISED OCTOBER 1998

15

Y0

14

Y1

G1

G2A

G2B

2

B

3

C

6

4

5

13

12

11

10

Y2

Y3

Data
Outputs

Y4

Y5

9

Y6

7

Y7

Select
Inputs

Enable

Inputs

Pin numbers shown are for the D, DB, J, PW, and W packages.

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V
Input voltage range, V
Output voltage range, V
Input clamp current, I
Output clamp current, I
Continuous output current, I
Continuous current through V
Package thermal impedance, θ

Storage temperature range, T

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.

2. The value of VCC is provided in the recommended operating conditions table.

3. The package thermal impedance is calculated in accordance with JESD 51.

–0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC

(see Note 1) –0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I

(see Notes 1 and 2) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

O

(VI < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

IK

(VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

OK

±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

O

or GND ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC

(see Note 3): D package 113°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

JA

DB package 131°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PW package 149°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

†

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3

SN54LVC138A, SN74LVC138A

UNIT

VCCSuppl

oltage

V

IOHHigh-level output current

mA

IOLLow-level output current

mA

3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS

SCAS291I – MARCH 1993 – REVISED OCTOBER 1998

recommended operating conditions (see Note 4)

SN54LVC138A SN74LVC138A

MIN MAX MIN MAX

pp

y v

V

V

V
V

∆t/∆v Input transition rise or fall rate 0 10 0 10 ns/V
T

NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,

High-level input voltage

IH

Low-level input voltage

IL

Input voltage 0 5.5 0 5.5 V

I

Output voltage 0 V

O

p

p

Operating free-air temperature –55 125 –40 85 °C

A

Implications of Slow or Floating CMOS Inputs

Operating 2 3.6 1.65 3.6
Data retention only 1.5 1.5
VCC = 1.65 V to 1.95 V 0.65 × V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V 2 2
VCC = 1.65 V to 1.95 V 0.35 × V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V 0.8 0.8

CC

VCC = 1.65 V –4
VCC = 2.3 V –8
VCC = 2.7 V –12 –12
VCC = 3 V –24 –24
VCC = 1.65 V 4
VCC = 2.3 V 8
VCC = 2.7 V 12 12
VCC = 3 V 24 24

, literature number SCBA004.

CC

1.7

0 V

0.7

CC

V

CC

V

V

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER

TEST CONDITIONS

V

UNIT

I

100 µA

I

mA

I

100 µA

V

V

SN54LVC138A, SN74LVC138A

3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS

SCAS291I – MARCH 1993 – REVISED OCTOBER 1998

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)

SN54LVC138A SN74LVC138A

MIN TYP†MAX MIN TYP†MAX

V

= –

OH

IOH = –4 mA 1.65 V 1.2

V

OH

OL

I

I

I

CC

∆I

CC

C

†

i

All typical values are at VCC = 3.3 V, TA = 25°C.

IOH = –8 mA 2.3 V 1.7

= –12

OH

IOH = –24 mA 3 V 2.2 2.2

=

OL

IOL = 4 mA 1.65 V 0.45
IOL = 8 mA 2.3 V 0.7
IOL = 12 mA 2.7 V 0.4 0.4
IOL = 24 mA 3 V 0.55 0.55
VI = 5.5 V or GND 3.6 V ±5 ±5 µA
VI = VCC or GND, IO = 0 3.6 V 10 10 µA
One input at VCC – 0.6 V,

Other inputs at VCC or GND
VI = VCC or GND 3.3 V 5 5 pF

CC

1.65 V to 3.6 V VCC–0.2

2.7 V to 3.6 V VCC–0.2

2.7 V 2.2 2.2
3 V 2.4 2.4

1.65 V to 3.6 V 0.2

2.7 V to 3.6 V 0.2

2.7 V to 3.6 V 500 500 µA

switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 3)

SN54LVC138A

PARAMETER

t

pd

FROM

(INPUT)

A or B or C 7.9 1 6.7

G2A or G2B

G1 6.4 1 5.8

TO

(OUTPUT)

Y

VCC = 2.7 V

MIN MAX MIN MAX

VCC = 3.3 V

± 0.3 V

7.4 1 6.5

UNIT

ns

switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 1 through 3)

SN74LVC138A

PARAMETER

t

pd

‡

t

sk(o)

‡

Skew between any two outputs of the same package switching in the same direction

FROM

(INPUT)

A or B or C 15.9 1 9.9 7.9 1 6.7

G2A or G2B

G1 14.4 1 8.4 6.4 1 5.8

TO

(OUTPUT)

Y

VCC = 1.8 V

TYP MIN MAX MIN MAX MIN MAX

15.4 1 9.4 7.4 1 6.5

VCC = 2.5 V

± 0.2 V

VCC = 2.7 V

VCC = 3.3 V

± 0.3 V

UNIT

ns

1 ns

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5

SN54LVC138A, SN74LVC138A

PARAMETER

UNIT

3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS

SCAS291I – MARCH 1993 – REVISED OCTOBER 1998

operating characteristics, T

C

Power dissipation capacitance f = 10 MHz 25 26 27 pF

pd

PARAMETER MEASUREMENT INFORMATION

From Output

Under Test

Timing

Input

Data

Input

Input

Output

CL = 30 pF

(see Note A)

t

PLH

PROPAGATION DELAY TIMES

VCC/2

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

VCC/2 VCC/2

VOLTAGE WAVEFORMS

1 kΩ

LOAD CIRCUIT

VCC/2

t

su

VCC/2 VCC/2

t

h

A

1 kΩ

= 25°C

VCC/2

S1

V

= 1.8 V ± 0.15 V

CC

2 × V

CC

Open

GND

V

CC

0 V

V

CC

0 V

V

CC

0 V

t

PHL

V

OH

V

OL

TEST

CONDITIONS

Control

(low-level

enabling)

Waveform 1

S1 at 2 × V

(see Note B)

Waveform 2

S1 at Open

(see Note B)

VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V

TYP TYP TYP

TEST S1

Input

Output

Output

CC

Output

t

pd

t

PLZ/tPZL

t

PHZ/tPZH

VOLTAGE WAVEFORMS

PULSE DURATION

t

PZL

VCC/2

t

PZH

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

t

VCC/2

Open

2 × V

Open

w

CC

VCC/2VCC/2

VCC/2VCC/2

t

PLZ

VOL + 0.15 V

t

PHZ

VOH – 0.15 V

V

0 V

V

0 V

V

V

V

0 V

CC

CC

CC

OL

OH

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. t
F. t

G. t

PLZ
PZL
PLH

and t
and t

and t

are the same as t

PHZ

are the same as ten.

PZH

are the same as tpd.

PHL

dis

Figure 1. Load Circuit and Voltage Waveforms

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

.

From Output

Under Test

CL = 30 pF

(see Note A)

SN54LVC138A, SN74LVC138A

3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS

SCAS291I – MARCH 1993 – REVISED OCTOBER 1998

PARAMETER MEASUREMENT INFORMATION

V

= 2.5 V ± 0.2 V

CC

2 × V

500 Ω

500 Ω

S1

Open

GND

CC

TEST S1

t

pd

t

PLZ/tPZL

t

PHZ/tPZH

Open

2 × V

GND

CC

LOAD CIRCUIT

Timing

Input

t

Data

Input

Input

t

PLH

Output

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.

E. t

PLZ

F. t

PZL

G. t

PLH

VCC/2

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

VCC/2 VCC/2

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

and t

PHZ

and t

PZH

and t

PHL

VCC/2

t

su

are the same as t
are the same as ten.
are the same as tpd.

h

VCC/2

VCC/2 VCC/2

.

dis

t

PHL

V

0 V

V

0 V

V

0 V

V

V

CC

CC

CC

OH

OL

Input

Output

Control

(low-level

enabling)

Output

Waveform 1

S1 at 2 × V

(see Note B)

Output

Waveform 2

S1 at GND

(see Note B)

VOLTAGE WAVEFORMS

PULSE DURATION

t

PZL

CC

t

PZH

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

VCC/2

VCC/2

t

w

V

0 V

V

0 V

V

V

V

0 V

CC

CC

CC

OL

OH

VCC/2VCC/2

VCC/2VCC/2

t

PLZ

VOL + 0.15 V

t

PHZ

VOH – 0.15 V

Figure 2. Load Circuit and Voltage Waveforms

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

7

SN54LVC138A, SN74LVC138A
3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS

SCAS291I – MARCH 1993 – REVISED OCTOBER 1998

PARAMETER MEASUREMENT INFORMATION

V

= 2.7 V AND 3.3 V ± 0.3 V

CC

6 V

From Output

Under Test

CL = 50 pF

(see Note A)

500 Ω

500 Ω

S1

Open

GND

TEST S1

t

pd

t

PLZ/tPZL

t

PHZ/tPZH

Open

6 V

GND

Timing

Input

Data

Input

Input

Output

t

PLH

LOAD CIRCUIT

1.5 V

t

su

1.5 V 1.5 V

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

1.5 V 1.5 V

1.5 V 1.5 V

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

t

h

t

PHL

2.7 V

0 V

2.7 V

0 V

2.7 V

0 V

V

OH

V

OL

Input

Output

Control

(low-level

enabling)

Output

Waveform 1

S1 at 6 V

(see Note B)

Output

Waveform 2

S1 at GND

(see Note B)

t

w

1.5 V 1.5 V

VOLTAGE WAVEFORMS

PULSE DURATION

1.5 V1.5 V

t

PZL

t

PLZ

1.5 V

t

t

PZH

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

PHZ

1.5 V

2.7 V

0 V

VOL + 0.3 V

VOH – 0.3 V

2.7 V

0 V

3 V

V

OL

V

OH

0 V

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤2.5 ns, tf ≤2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. t
F. t

G. t

PLZ
PZL
PLH

and t
and t

and t

are the same as t

PHZ

are the same as ten.

PZH

are the same as tpd.

PHL

dis

Figure 3. Load Circuit and Voltage Waveforms

8

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.

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