Datasheet SN74LV165AD, SN74LV165ADBR, SN74LV165ADGVR, SN74LV165ADR, SN74LV165APWR Datasheet (Texas Instruments)
Page 1
OPERATION
SN54LV165A, SN74LV165A
PARALLEL-LOAD 8-BIT SHIFT REGISTERS
SCLS402B – APRIL 1998 – REVISED JUL Y 1998
D
EPIC
(Enhanced-Performance Implanted
CMOS) Process
D
Typical V
< 0.8 V at V
D
Typical V
< 2 V at V
D
Latch-Up Performance Exceeds 250 mA Per
(Output Ground Bounce)
OLP
, TA = 25°C
CC
(Output VOH Undershoot)
OHV
, TA = 25°C
CC
JESD 17
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D
Package Options Include Plastic
Small-Outline (D, NS), Shrink Small-Outline
(DB), Thin Very Small-Outline (DGV), and
SN74LV165A. . . D, DB, DGV, NS, OR PW PACKAGE
SN54LV165A...J OR W PACKAGE
(TOP VIEW)
SH/LD
GND
SN54LV165A. . . FK PACKAGE
CLK
Q
E
F
G
H
H
1
2
3
4
5
6
7
8
(TOP VIEW)
16
15
14
13
12
11
10
9
V
CC
CLK INH
D
C
B
A
SER
Q
H
Thin Shrink Small-Outline (PW) Packages,
Ceramic Flat (W) Packages, Chip Carriers
(FK), and DIPs (J)
description
4
The ’LV165A devices are parallel-load, 8-bit shift
registers designed for 2-V to 5.5-V V
operation.
CC
When the device is clocked, data is shifted toward
the serial output Q
. Parallel-in access to each
H
stage is provided by eight individual direct data
inputs that are enabled by a low level at the
shift/load (SH/LD
) input. The ’LV165A devices
feature a clock inhibit function and a
complemented serial output Q
.
H
Clocking is accomplished by a low-to-high transition of the clock (CLK) input while SH/LD
E
5
F
6
NC
7
G
8
H
NC – No internal connection
CLK
3212019
910111213
H
Q
SH/LD
NC
NC
GND
CC
V
CLK INH
D
18
17
C
16
NC
15
B
14
A
H
Q
SER
is held high and clock
inhibit (CLK INH) is held low. The functions of the CLK and CLK INH inputs are interchangeable. Since a low
CLK input and a low-to-high transition of CLK INH accomplishes clocking, CLK INH should be changed to the
high level only while CLK is high. Parallel loading is inhibited when SH/LD
the register are enabled while SH/LD
is held low, independently of the levels of CLK, CLK INH, or SER.
is held high. The parallel inputs to
The SN54L V165A is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74LV165A is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
INPUTS
SH/LD CLK CLK INH
L X X Parallel load
H HX Q
HXH Q
HL↑ Shift
H ↑ L Shift
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
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0
Copyright 1998, Texas Instruments Incorporated
1
Page 2
SN54LV165A, SN74LV165A
PARALLEL-LOAD 8-BIT SHIFT REGISTERS
SCLS402B – APRIL 1998 – REVISED JUL Y 1998
logic diagram (positive logic)
ABCDEFGH
11 12 13 14 3 4 5 6
SH/LD
1
CLK
SER
15
2
10
S
1D
R
C1
S
1D
R
C1
S
1D
R
C1
CLK INH
Pin numbers shown are for the D, DB, DGV , J, NS, PW, and W packages.
typical shift, load, and inhibit sequences
CLK
CLK INH
SER
SH/LD
A
L
H
S
1D
R
C1
S
1D
R
C1
S
1D
R
C1
S
1D
R
C1
S
1D
R
C1
9
Q
H
7
Q
H
Data
Inputs
B
C
D
E
F
G
H
Q
H
Q
H
L
H
L
H
L
H
H
L
H
H
L
L
H
L
H
L
H
L
H
L
H
L
H
Serial ShiftInhibit
Load
2
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Page 3
UNIT
VIHHigh-level input voltage
V
VILLow-level input voltage
V
IOHHigh-level output current
IOLLow-level output current
SN54LV165A, SN74LV165A
PARALLEL-LOAD 8-BIT SHIFT REGISTERS
SCLS402B – APRIL 1998 – REVISED JUL Y 1998
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
Input voltage range, V
Output voltage range, V
Input clamp current, I
Output clamp current, I
Continuous output current, I
Continuous current through V
Package thermal impedance, θ
–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
(see Notes 1 and 2) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
(VI < 0) –20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IK
(VO < 0 or VO > VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OK
(VO = 0 to VCC) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
or GND ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
(see Note 3): D package 113°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
†
DB package 131°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DGV package 180°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NS package 11 1° C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 149°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 7 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51.
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
recommended operating conditions (see Note 4)
SN54LV165A SN74LV165A
MIN MAX MIN MAX
V
V
V
∆t/∆v Input transition rise or fall rate
T
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Supply voltage 2 5.5 2 5.5 V
CC
VCC = 2 V 1.5 1.5
p
p
Input voltage 0 5.5 0 5.5 V
I
Output voltage 0 V
O
p
p
Operating free-air temperature –55 125 –40 85 °C
A
Implications of Slow or Floating CMOS Inputs
VCC = 2.3 V to 2.7 V VCC × 0.7 VCC × 0.7
VCC = 3 V to 3.6 V VCC × 0.7 VCC × 0.7
VCC = 4.5 V to 5.5 V VCC × 0.7 VCC × 0.7
VCC = 2 V 0.5 0.5
VCC = 2.3 V to 2.7 V VCC × 0.3 VCC × 0.3
VCC = 3 V to 3.6 V VCC × 0.3 VCC × 0.3
VCC = 4.5 V to 5.5 V VCC × 0.3 VCC × 0.3
CC
VCC = 2 V –50 –50 µ A
VCC = 2.3 V to 2.7 V –2 –2
VCC = 3 V to 3.6 V –6 –6
VCC = 4.5 V to 5.5 V –12 –12
VCC = 2 V 50 50 µA
VCC = 2.3 V to 2.7 V 2 2
VCC = 3 V to 3.6 V 6 6
VCC = 4.5 V to 5.5 V 12 12
VCC = 2.3 V to 2.7 V 0 200 0 200
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V 0 20 0 20
, literature number SCBA004.
0 100 0 100
0 V
CC
V
mA
mA
ns/V
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
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SN54LV165A, SN74LV165A
PARAMETER
TEST CONDITIONS
V
UNIT
V
V
V
V
UNIT
twPulse duration
ns
t
Set
ns
UNIT
twPulse duration
ns
t
Set
ns
PARALLEL-LOAD 8-BIT SHIFT REGISTERS
SCLS402B – APRIL 1998 – REVISED JUL Y 1998
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54LV165A SN74LV165A
MIN TYP MAX MIN TYP MAX
I
I
I
C
OH
OL
I
CC
off
i
CC
IOH = –50 µA 2 V to 5.5 V VCC–0.1 VCC–0.1
IOH = –2 mA 2.3 V 2 2
IOH = –6 mA 3 V 2.48 2.48
IOH = –12 mA 4.5 V 3.8 3.8
IOL = 50 µA 2 V to 5.5 V 0.1 0.1
IOL = 2 mA 2.3 V 0.4 0.4
IOL = 6 mA 3 V 0.44 0.44
IOL = 12 mA 4.5 V 0.55 0.55
VI = VCC or GND 5.5 V ±1 ±1 µA
VI = VCC or GND, IO = 0 5.5 V 20 20 µA
VI or VO = 0 to 5.5 V 0 V 5 5 µA
VI = VCC or GND 3.3 V 1.7 1.7 pF
timing requirements over recommended operating free-air temperature range, V
(unless otherwise noted) (see Figure 1)
TA = 25°C SN54LV165A SN74LV165A
MIN MAX MIN MAX MIN MAX
CLK high or low 8.5 9 9
SH/LD low 11 13 13
SH/LD high before CLK↑ 7 8.5 8.5
su
t
h
up time
Hold time
SER before CLK↑ 8.5 9.5 9.5
CLK INH before CLK↑
Data before SH/LD↑ 11.5 12 12
SER data after CLK↑ –1 0 0
Parallel data after SH/LD
SH/LD high after CLK↑ 0 0 0
↑ 0 0.5 0.5
7 7 7
timing requirements over recommended operating free-air temperature range, V
(unless otherwise noted) (see Figure 1)
TA = 25°C SN54LV165A SN74LV165A
MIN MAX MIN MAX MIN MAX
CLK high or low 6 7 7
SH/LD low 7.5 9 9
SH/LD high before CLK↑ 5 6 6
su
t
h
up time
Hold time
SER before CLK↑ 5 6 6
CLK INH before CLK↑
Data before SH/LD↑ 7.5 8.5 8.5
SER data after CLK↑ 0 0 0
Parallel data after SH/LD
SH/LD high after CLK↑ 0 0 0
↑ 0.5 0.5 0.5
5 5 5
= 2.5 V ±0.2 V
CC
= 3.3 V ±0.3 V
CC
ns
ns
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
4
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UNIT
twPulse duration
ns
t
Set
ns
PARAMETER
UNIT
f
MH
PARAMETER
UNIT
f
MH
HH
L
SN54LV165A, SN74LV165A
PARALLEL-LOAD 8-BIT SHIFT REGISTERS
SCLS402B – APRIL 1998 – REVISED JUL Y 1998
timing requirements over recommended operating free-air temperature range, V
CC
(unless otherwise noted) (see Figure 1)
TA = 25°C SN54LV165A SN74LV165A
MIN MAX MIN MAX MIN MAX
CLK high or low 4 4 4
SH/LD low 5 6 6
SH/LD high before CLK↑ 4 4 4
su
t
h
up time
Hold time
SER before CLK↑ 4 4 4
CLK INH before CLK↑
Data before SH/LD↑ 5 5 5
SER data after CLK↑ 0.5 0.5 0.5
Parallel data after SH/LD
SH/LD high after CLK↑ 0.5 0.5 0.5
↑ 1 1 1
3.5 3.5 3.5
switching characteristics over recommended operating free-air temperature range,
= 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1)
V
CC
FROM TO LOAD
(INPUT) (OUTPUT) CAPACITANCE
max
CLK 12.2 19.8 1 22 1 22
tpd*
t
pd
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
SH/LD
H 12.9 21.7 1 24 1 24
CLK 15.3 23.3 1 26 1 26
SH/LD
H 15.9 25.3 1 28 1 28
QH or Q
QH or Q
H
H
CL = 15 pF* 50 80 45 45
CL = 50 pF 40 65 35 35
CL = 15 pF
CL = 50 pF
TA = 25°C SN54LV165A SN74LV165A
MIN TYP MAX MIN MAX MIN MAX
13.1 21.5 1 23.5 1 23.5
16.1 25.1 1 28 1 28
= 5 V ± 0.5 V
ns
ns
ns
z
switching characteristics over recommended operating free-air temperature range,
= 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
V
CC
FROM TO LOAD
(INPUT) (OUTPUT) CAPACITANCE
max
CLK 8.6 15.4 1 18 1 18
tpd*
t
pd
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SH/LD
H
CLK 10.9 18.9 1 21.5 1 21.5
SH/LD
H 11.1 17.6 1 20 1 20
QH or Q
QH or Q
H
H
CL = 15 pF* 65 115 55 55
CL = 50 pF 60 90 50 50
CL = 15 pF
CL = 50 pF
TA = 25°C SN54LV165A SN74LV165A
MIN TYP MAX MIN MAX MIN MAX
9.1 15.8 1 18.5 1 18.5
8.9 14.1 1 16.5 1 16.5
11.3 19.3 1 22 1 22
z
ns
ns
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SN54LV165A, SN74LV165A
PARAMETER
UNIT
f
MH
HH
L
C
d
Power dissi ation ca acitance
C
L
MHz
F
PARALLEL-LOAD 8-BIT SHIFT REGISTERS
SCLS402B – APRIL 1998 – REVISED JUL Y 1998
switching characteristics over recommended operating free-air temperature range,
= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
V
CC
FROM TO LOAD
(INPUT) (OUTPUT) CAPACITANCE
max
CLK 6 9.9 1 11.5 1 11.5
tpd*
t
pd
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
SH/LD
H
CLK 7.7 11.9 1 13.5 1 13.5
SH/LD
H 7.6 11 1 12.5 1 12.5
QH or Q
QH or Q
H
H
CL = 15 pF* 110 165 90 90
CL = 50 pF 95 125 85 85
CL = 15 pF
CL = 50 pF
operating characteristics, TA = 25°C
PARAMETER TEST CONDITIONS V
p
p
p
TA = 25°C SN54LV165A SN74LV165A
MIN TYP MAX MIN MAX MIN MAX
6 9.9 1 11.5 1 11.5
6 9 1 10.5 1 10.5
7.7 11.9 1 13.5 1 13.5
CC
p
= 50 F,f = 10
3.3 V 36.1
5 V 37.5
z
ns
ns
TYP UNIT
p
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
6
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Page 7
From Output
Under Test
(see Note A)
SN54LV165A, SN74LV165A
PARALLEL-LOAD 8-BIT SHIFT REGISTERS
SCLS402B – APRIL 1998 – REVISED JUL Y 1998
PARAMETER MEASUREMENT INFORMATION
V
Test
Point
C
L
From Output
Under Test
(see Note A)
C
L
RL = 1 kΩ
S1
CC
Open
GND
TEST S1
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
Open Drain
Open
V
CC
GND
V
CC
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
t
w
Input
Input
In-Phase
Output
Out-of-Phase
Output
INVERTING AND NONINVERTING OUTPUTS
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
E. t
F. t
G. t
50% V
CC
VOLTAGE WAVEFORMS
PULSE DURATION
50% V
CC
t
PLH
50% V
CC
t
PHL
50% V
CC
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
PLZ
PZL
PHL
and t
and t
and t
are the same as t
PHZ
are the same as ten.
PZH
are the same as tpd.
PLH
3-STATE AND OPEN-DRAIN OUTPUTS
50% V
50% V
dis
CC
t
PHL
50% V
t
PLH
50% V
.
LOAD CIRCUIT FOR
V
CC
CC
0 V
V
CC
0 V
V
OH
CC
V
OL
V
OH
CC
V
OL
Timing Input
Data Input
Output
Control
Output
Waveform 1
S1 at V
(see Note B)
Waveform 2
(see Note B)
CC
Output
S1 at GND
50% V
CC
t
CC
CC
h
50% V
50% V
VOL + 0.3 V
VOH – 0.3 V
CC
CC
t
su
50% V
CC
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
50% V
CC
t
PZL
t
PZH
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
t
PLZ
50% V
t
PHZ
50% V
V
CC
0 V
V
CC
0 V
V
CC
0 V
≈ V
V
OL
V
OH
≈ 0 V
CC
Figure 1. Load Circuit and Voltage Waveforms
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any product or service without notice, and advise customers to obtain the latest version of relevant information
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
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