Datasheet SN74LV139ADR, SN74LV139APWR, SN74LV139AD, SN74LV139ADBR, SN74LV139ADGVR Datasheet (Texas Instruments)

SN54LV139A, SN74LV139A

DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS

SCLS396A – APRIL 1998 – REVISED OCTOBER 1998

D

EPIC

 (Enhanced-Performance Implanted

CMOS) Process

D

Designed Specifically for High-Speed
Memory Decoders and Data-Transmission
Systems

D

Incorporate Two Enable Inputs to Simplify
Cascading and/or Data Reception

D

Latch-Up Performance Exceeds 250 mA Per
JESD 17

D

ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V

SN74LV139A. . . D, DB, DGV, NS, OR PW PACKAGE

SN54LV139A...J OR W PACKAGE

(TOP VIEW)

1G

1A

1B
1Y0
1Y1
1Y2
1Y3

GND

1
2
3
4
5
6
7
8

16
15
14
13
12
11
10

V

CC

2G
2A
2B
2Y0
2Y1
2Y2

9

2Y3

Using Machine Model (C = 200 pF, R = 0)

D

Package Options Include Plastic
Small-Outline (D, NS), Shrink Small-Outline
(DB), Thin Very Small-Outline (DGV), and
Thin Shrink Small-Outline (PW) Packages,
Ceramic Flat (W) Packages, Chip Carriers
(FK), and DIPs (J)

description

The ’LV139A devices are dual 2-line to 4-line
decoders/demultiplexers designed for 2-V to

5.5-V V
These devices are designed for high-performance

memory-decoding or data-routing applications
requiring very short propagation delay times. In

operation.

CC

SN54LV139A. . . FK PACKAGE

1B

1Y0

NC
1Y1
1Y2

NC – No internal connection

(TOP VIEW)

1A1GNC

3212019

4
5
6
7
8

910111213

NC

1Y3

GND

CC

V

2Y3

2G

18
17
16
15
14

2Y2

2A
2B
NC
2Y0
2Y1

high-performance memory systems, these
decoders can minimize the effects of system decoding. When employed with high-speed memories utilizing a
fast enable circuit, the delay time of these decoders and the enable time of the memory are usually less than
the typical access time of the memory . This means that the effective system delay introduced by the decoders
is negligible.

The ’LV139A devices comprise two individual 2-line to 4-line decoders in a single package. The active-low
enable (G

) input can be used as a data line in demultiplexing applications. These decoders/demultiplexers

feature fully buffered inputs, each of which represents only one normalized load to its driving circuit.
The SN54LV139A is characterized for operation over the full military temperature range of –55°C to 125°C.

The SN74LV139A is characterized for operation from –40°C to 85°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  1998, Texas Instruments Incorporated

1

SN54LV139A, SN74LV139A

OUTPUTS

G

DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS

SCLS396A – APRIL 1998 – REVISED OCTOBER 1998

FUNCTION TABLE

INPUTS

SELECT

B A Y0 Y1 Y2 Y3

H X X H H H H

L L LLHHH
LLHHLHH
LHLHHLH

LHHHHHL

logic symbols (alternatives)

X/Y

2

1A

3

1B

1

1G

14

2A

13

2B

15

2G

†

These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

Pin numbers shown are for the D, DB, DGV, J, NS, PW, and W packages.

1
2
EN

†

4

12
11

10

1Y0

5

1Y1

6

1Y2

7

1Y3

2Y0
2Y1

2Y2

9

2Y3

1A
1B

1G

2A
2B

2G

2
3
1

14
13
15

0
1

2

3

DMUX

0

G

1

0

0

1

3

2
3

12
11
10

4

1Y0

5

1Y1

6

1Y2

7

1Y3
2Y0

2Y1
2Y2

9

2Y3

2

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logic diagram (positive logic)

SN54LV139A, SN74LV139A

DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS

SCLS396A – APRIL 1998 – REVISED OCTOBER 1998

4

1Y0

1

1G

2

1A

3

1B

15

2G

14

2A

13

2B

Pin numbers shown are for the D, DB, DGV , J, NS, PW, and W packages.

12

11

10

5

1Y1

6

1Y2

7

1Y3

2Y0

2Y1

2Y2

9

2Y3

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

†

Supply voltage range, V
Input voltage range, V
Output voltage range, V
Input clamp current, I
Output clamp current, I
Continuous output current, I
Continuous current through V
Package thermal impedance, θ

–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC

(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I

(see Notes 1 and 2) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

O

(VI < 0) –20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

IK

(VO < 0 or VO > VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

OK

(VO = 0 to VCC) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

O

or GND ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC

(see Note 3): D package 113°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

JA

DB package 131°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DGV package 180°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

NS package 11 1° C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PW package 149°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

2. This value is limited to 7 V maximum.

3. The package thermal impedance is calculated in accordance with JESD 51.

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

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3

SN54LV139A, SN74LV139A

UNIT

VIHHigh-level input voltage

V

VILLow-level input voltage

V

IOHHigh-level output current

IOLLow-level output current

PARAMETER

TEST CONDITIONS

V

UNIT

V

V

V

V

DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS

SCLS396A – APRIL 1998 – REVISED OCTOBER 1998

recommended operating conditions (see Note 4)

SN54LV139A SN74LV139A

MIN MAX MIN MAX

V

V
V

∆t/∆v Input transition rise or fall rate

T

NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,

Supply voltage 2 5.5 2 5.5 V

CC

VCC = 2 V 1.5 1.5

p

p

Input voltage 0 5.5 0 5.5 V

I

Output voltage 0 V

O

p

p

Operating free-air temperature –55 125 –40 85 °C

A

Implications of Slow or Floating CMOS Inputs

VCC = 2.3 V to 2.7 V VCC × 0.7 VCC × 0.7
VCC = 3 V to 3.6 V VCC × 0.7 VCC × 0.7
VCC = 4.5 V to 5.5 V VCC × 0.7 VCC × 0.7
VCC = 2 V 0.5 0.5
VCC = 2.3 V to 2.7 V VCC × 0.3 VCC × 0.3
VCC = 3 V to 3.6 V VCC × 0.3 VCC × 0.3
VCC = 4.5 V to 5.5 V VCC × 0.3 VCC × 0.3

CC

VCC = 2 V –50 –50 µA
VCC = 2.3 V to 2.7 V –2 –2
VCC = 3 V to 3.6 V –6 –6
VCC = 4.5 V to 5.5 V –12 –12
VCC = 2 V 50 50 µA
VCC = 2.3 V to 2.7 V 2 2
VCC = 3 V to 3.6 V 6 6
VCC = 4.5 V to 5.5 V 12 12
VCC = 2.3 V to 2.7 V 0 200 0 200
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V 0 20 0 20

, literature number SCBA004.

0 100 0 100

0 V

CC

V

mA

mA

ns/V

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)

SN54LV139A SN74LV139A

MIN TYP MAX MIN TYP MAX

IOH = –50 µA 2 V to 5.5 V VCC–0.1 VCC–0.1

OH

OL

I

I

I

CC

I

off

C

i

PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.

IOH = –2 mA 2.3 V 2 2
IOH = –6 mA 3 V 2.48 2.48
IOH = –12 mA 4.5 V 3.8 3.8
IOL = 50 µA 2 V to 5.5 V 0.1 0.1
IOL = 2 mA 2.3 V 0.4 0.4
IOL = 6 mA 3 V 0.44 0.44
IOL = 12 mA 4.5 V 0.55 0.55
VI = VCC or GND 5.5 V ±1 ±1 µA
VI = VCC or GND, IO = 0 5.5 V 20 20 µA
VI or VO = 0 to 5.5 V 0 V 5 5 µA
VI = VCC or GND 3.3 V 1.9 1.9 pF

CC

4

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PARAMETER

UNIT

tpd*

C

pF

ns

t

C

pF

ns

PARAMETER

UNIT

tpd*

C

15 pF

ns

t

C

pF

ns

PARAMETER

UNIT

tpd*

C

pF

ns

t

C

pF

ns

CpdPower dissipation capacitance

C

50 pF

pF

SN54LV139A, SN74LV139A

DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS

SCLS396A – APRIL 1998 – REVISED OCTOBER 1998

switching characteristics over recommended operating free-air temperature range,

= 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1)

V

CC

FROM TO LOAD

(INPUT) (OUTPUT) CAPACITANCE

*

pd

* On products compliant to MIL-PRF-38535, this parameter is not production tested.

A or B Y

G Y

A or B Y

G Y

= 15

L

= 50

L

p

p

switching characteristics over recommended operating free-air temperature range,

= 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)

V

CC

FROM TO LOAD

(INPUT) (OUTPUT) CAPACITANCE

*

pd

* On products compliant to MIL-PRF-38535, this parameter is not production tested.

A or B Y

G Y

A or B Y

G Y

=

L

= 50

L

p

p

TA = 25°C SN54LV139A SN74LV139A

MIN TYP MAX MIN MAX MIN MAX

7.7 17.6 1 21 1 21

7.4 15.8 1 19 1 19

10.2 22.5 1 26.5 1 26.5

9.9 20.2 1 24 1 24

TA = 25°C SN54LV139A SN74LV139A

MIN TYP MAX MIN MAX MIN MAX

5.3 11 1 13 1 13

5.1 9.2 1 11 1 11

7.3 14.5 1 16.5 1 16.5
7 12.7 1 14.5 1 14.5

switching characteristics over recommended operating free-air temperature range,

= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)

V

CC

FROM TO LOAD

(INPUT) (OUTPUT) CAPACITANCE

*

pd

* On products compliant to MIL-PRF-38535, this parameter is not production tested.

A or B Y

G Y

A or B Y

G Y

= 15

L

= 50

L

p

p

TA = 25°C SN54LV139A SN74LV139A

MIN TYP MAX MIN MAX MIN MAX

3.7 7.2 1 8.5 1 8.5

3.5 6.3 1 7.5 1 7.5

5.2 9.2 1 10.5 1 10.5

4.9 8.3 1 9.5 1 9.5

operating characteristics, TA = 25°C

PARAMETER

p

p

TEST CONDITIONS V

p

,f = 10 MHz

=

L

CC

3.3 V 17.3
5 V 18.2

TYP UNIT

p

PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5

SN54LV139A, SN74LV139A
DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS

SCLS396A – APRIL 1998 – REVISED OCTOBER 1998

PARAMETER MEASUREMENT INFORMATION

From Output

Under Test

(see Note A)

Test
Point

C

L

From Output

Under Test

(see Note A)

C

L

RL = 1 kΩ

S1

V

CC

GND

Open

TEST S1

t

PLH/tPHL

t

PLZ/tPZL

t

PHZ/tPZH

Open Drain

Open

V

CC

GND
V

CC

LOAD CIRCUIT FOR

TOTEM-POLE OUTPUTS

t

w

Input

Input

In-Phase

Output

Out-of-Phase

Output

INVERTING AND NONINVERTING OUTPUTS

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
E. t
F. t

G. t

50% V

CC

VOLTAGE WAVEFORMS

PULSE DURATION

50% V

CC

t

PLH

50% V

CC

t

PHL

50% V

CC

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

PLZ
PZL
PHL

and t
and t

and t

are the same as t

PHZ

are the same as ten.

PZH

are the same as tpd.

PLH

3-STATE AND OPEN-DRAIN OUTPUTS

50% V

50% V

dis

CC

t

PHL

50% V

t

PLH

50% V

.

LOAD CIRCUIT FOR

V

CC

CC

0 V

V

CC

0 V

V

OH

CC

V

OL

V

OH

CC

V

OL

Timing Input

Data Input

Output

Control

Output

Waveform 1

S1 at V

(see Note B)

Waveform 2

(see Note B)

CC

Output

S1 at GND

50% V

CC

t

CC

CC

h

50% V

50% V

CC

CC

VOL + 0.3 V

VOH – 0.3 V

t

su

50% V

CC

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

50% V

CC

t

PZL

t

PZH

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

LOW- AND HIGH-LEVEL ENABLING

t

PLZ

50% V

t

PHZ

50% V

V

CC

0 V

V

CC

0 V

V

CC

0 V

≈ V

V

OL

V

OH

≈ 0 V

CC

Figure 1. Load Circuit and Voltage Waveforms

6

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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
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Copyright  1998, Texas Instruments Incorporated