Datasheet SN74LV138AD, SN74LV138ADBR, SN74LV138ADGVR, SN74LV138ADR, SN74LV138APWR Datasheet (Texas Instruments)

SN54LV138A, SN74LV138A

3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS

SCLS395B – APRIL 1998 – REVISED JUL Y 1998

D

EPIC

 (Enhanced-Performance Implanted

CMOS) Process

D

Typical V
< 0.8 V at V

D

Typical V
> 2 V at V

D

Latch-Up Performance Exceeds 250 mA Per

(Output Ground Bounce)

OLP

, TA = 25°C

CC

(Output VOH Undershoot)

OHV

, TA = 25°C

CC

JESD 17

D

ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)

D

Package Options Include Plastic
Small-Outline (D, NS), Shrink Small-Outline
(DB), Thin Very Small-Outline (DGV), and
Thin Shrink Small-Outline (PW) Packages,
Ceramic Flat (W) Packages, Chip Carriers
(FK), and DIPs (J)

description

The ’LV138A devices are 3-line to 8-line
decoders/demultiplexers designed for 2-V to

5.5-V V
These devices are designed for high-

performance memory-decoding or data-routing
applications requiring very short propagation
delay times. In high-performance memory

operation.

CC

SN74LV138A. . . D, DB, DGV, NS, OR PW PACKAGE

SN54LV138A...J OR W PACKAGE

(TOP VIEW)

NC

16
15
14
13
12
11
10

9

CC

V

Y6

V
Y0
Y1
Y2
Y3
Y4
Y5
Y6

Y0

18
17
16
15
14

Y5

CC

Y1
Y2
NC
Y3
Y4

A

1

B

2

C

3

G2A

4
5

G2B

6

G1

7

Y7

GND

SN54LV138A. . . FK PACKAGE

C

G2A

NC

G2B

G1

NC – No internal connection

8

(TOP VIEW)

BANC

3212019

4
5
6
7
8

910111213

Y7

GND

systems, this decoder can be used to minimize the
effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay
times of this decoder and the enable time of the memory are usually less than the typical access time of the
memory. This means that the effective system delay introduced by the decoder is negligible.

The conditions at the binary-select inputs (A, B, C) and the three enable inputs (G1, G2A
eight output lines. The two active-low (G2A

, G2B) and one active-high (G1) enable inputs reduce the need for

, G2B) select one of

external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters
and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing
applications.

The SN54L V138A is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74LV138A is characterized for operation from –40°C to 85°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC is a trademark of Texas Instruments Incorporated.

UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.

Copyright  1998, Texas Instruments Incorporated

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

1

SN54LV138A, SN74LV138A
3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS

SCLS395B – APRIL 1998 – REVISED JUL Y 1998

FUNCTION TABLE

ENABLE INPUTS

G1 G2A G2B C B A Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7

X H X X X X H H H H H H H H
X XHXXXHHHHHHHH
LXXXXXHHHHHHHH
HLLLLLLHHHHHHH
HLLLLHHLHHHHHH
HLLLHLHHLHHHHH
HLLLHHHHHLHHHH
HLLHLLHHHHLHHH
HLLHLHHHHHHLHH
HLLHHLHHHHHHLH
HL LHHHHHHHHHHL

SELECT INPUTS OUTPUTS

logic symbols (alternatives)

1

A

2

B

3

C

6

G1

4

G2A

5

G2B

†

These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

Pin numbers shown are for the D, DB, DGV, J, NS, PW, and W packages.

BIN/OCT

1
2
4

&

EN

†

15

0
1
2
3
4
5
6
7

14
13
12
11
10

Y0
Y1
Y2
Y3
Y4
Y5

9

Y6

7

Y7

G1
G2A
G2B

1

A

2

B

3

C

6
4

5

DMUX

0

G

2

&

0

0

1

7

2
3
4
5
6
7

15
14
13
12
11
10

Y0
Y1
Y2
Y3
Y4
Y5

9

Y6

7

Y7

2

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logic diagram (positive logic)

1

A

SN54LV138A, SN74LV138A

3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS

SCLS395B – APRIL 1998 – REVISED JUL Y 1998

15

Y0

14

Y1

G1

G2A

G2B

2

B

3

C

6

4

5

13

12

11

10

Y2

Y3

Data
Outputs

Y4

Y5

9

Y6

7

Y7

Select
Inputs

Enable

Inputs

Pin numbers shown are for the D, DB, DGV, J, NS, PW, and W packages.

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

†

Supply voltage range, V
Input voltage range, V
Output voltage range, V
Input clamp current, I
Output clamp current, I
Continuous output current, I
Continuous current through V
Package thermal impedance, θ

–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC

(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I

(see Notes 1 and 2) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

O

(VI < 0) –20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

IK

(VO < 0 or VO > VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

OK

(VO = 0 to VCC) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

O

or GND ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC

(see Note 3): D package 113°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

JA

DB package 131°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DGV package 180°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

NS package 11 1° C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PW package 149°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

2. This value is limited to 7 V maximum.

3. The package thermal impedance is calculated in accordance with JESD 51.

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

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3

SN54LV138A, SN74LV138A

UNIT

VIHHigh-level input voltage

V

VILLow-level input voltage

V

IOHHigh-level output current

IOLLow-level output current

PARAMETER

TEST CONDITIONS

V

UNIT

V

V

V

V

3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS

SCLS395B – APRIL 1998 – REVISED JUL Y 1998

recommended operating conditions (see Note 4)

SN54LV138A SN74LV138A

MIN MAX MIN MAX

V

V
V

∆t/∆v Input transition rise or fall rate

T

NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,

Supply voltage 2 5.5 2 5.5 V

CC

VCC = 2 V 1.5 1.5

p

p

Input voltage 0 5.5 0 5.5 V

I

Output voltage 0 V

O

p

p

Operating free-air temperature –55 125 –40 85 °C

A

Implications of Slow or Floating CMOS Inputs

VCC = 2.3 V to 2.7 V VCC × 0.7 VCC × 0.7
VCC = 3 V to 3.6 V VCC × 0.7 VCC × 0.7
VCC = 4.5 V to 5.5 V VCC × 0.7 VCC × 0.7
VCC = 2 V 0.5 0.5
VCC = 2.3 V to 2.7 V VCC × 0.3 VCC × 0.3
VCC = 3 V to 3.6 V VCC × 0.3 VCC × 0.3
VCC = 4.5 V to 5.5 V VCC × 0.3 VCC × 0.3

CC

VCC = 2 V –50 –50 µA
VCC = 2.3 V to 2.7 V –2 –2
VCC = 3 V to 3.6 V –6 –6
VCC = 4.5 V to 5.5 V –12 –12
VCC = 2 V 50 50 µA
VCC = 2.3 V to 2.7 V 2 2
VCC = 3 V to 3.6 V 6 6
VCC = 4.5 V to 5.5 V 12 12
VCC = 2.3 V to 2.7 V 0 200 0 200
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V 0 20 0 20

, literature number SCBA004.

0 100 0 100

0 V

CC

V

mA

mA

ns/V

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)

SN54LV138A SN74LV138A

MIN TYP MAX MIN TYP MAX

IOH = –50 µA 2 V to 5.5 V VCC–0.1 VCC–0.1

OH

OL

I

I

I

CC

I

off

C

i

PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.

IOH = –2 mA 2.3 V 2 2
IOH = –6 mA 3 V 2.48 2.48
IOH = –12 mA 4.5 V 3.8 3.8
IOL = 50 µA 2 V to 5.5 V 0.1 0.1
IOL = 2 mA 2.3 V 0.4 0.4
IOL = 6 mA 3 V 0.44 0.44
IOL = 12 mA 4.5 V 0.55 0.55
VI = VCC or GND 5.5 V ±1 ±1 µA
VI = VCC or GND, IO = 0 5.5 V 20 20 µA
VI or VO = 0 to 5.5 V 0 V 5 5 µA
VI = VCC or GND 3.3 V 2.1 2.1 pF

CC

4

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PARAMETER

UNIT

PARAMETER

UNIT

PARAMETER

UNIT

C

d

Power dissi ation ca acitance

C

L

MHz

F

SN54LV138A, SN74LV138A

3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS

SCLS395B – APRIL 1998 – REVISED JUL Y 1998

switching characteristics over recommended operating free-air temperature range,

= 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1)

V

CC

FROM TO LOAD

(INPUT) (OUTPUT) CAPACITANCE

A, B, or C 11.7 17.6 1 21 1 21

tpd*

t

pd

* On products compliant to MIL-PRF-38535, this parameter is not production tested.

G1

G2A or G2B 11.4 18.2 1 21 1 21

A, B, or C 14.9 21.4 1 25 1 25

G1

G2A or G2B 14.8 22 1 25 1 25

Y CL = 15 pF

Y CL = 50 pF

switching characteristics over recommended operating free-air temperature range,

= 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)

V

CC

FROM TO LOAD

(INPUT) (OUTPUT) CAPACITANCE

A, B, or C 8.1 11.4 1 13 1 13

tpd*

t

pd

* On products compliant to MIL-PRF-38535, this parameter is not production tested.

G1

G2A or G2B 7.8 11.4 1 13.5 1 13.5

A, B, or C 10.3 15.8 1 18 1 18

G1

G2A or G2B 10 14.9 1 17 1 17

Y CL = 15 pF

Y CL = 50 pF

TA = 25°C SN54LV138A SN74LV138A

MIN TYP MAX MIN MAX MIN MAX

12.3 19.2 1 22 1 22

15.7 22.6 1 26 1 26

TA = 25°C SN54LV138A SN74LV138A

MIN TYP MAX MIN MAX MIN MAX

8.4 12.8 1 15 1 15

10.6 16.3 1 18.5 1 18.5

ns

ns

ns

ns

switching characteristics over recommended operating free-air temperature range,

= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)

V

CC

FROM TO LOAD

(INPUT) (OUTPUT) CAPACITANCE

A, B, or C 5.6 8.1 1 9.5 1 9.5

tpd*

t

pd

* On products compliant to MIL-PRF-38535, this parameter is not production tested.

G1

G2A or G2B 5.4 8.1 1 9.5 1 9.5

A, B, or C 7 10.1 1 11.5 1 11.5

G1

G2A or G2B 6.8 10.1 1 11.5 1 11.5

Y CL = 15 pF

Y CL = 50 pF

TA = 25°C SN54LV138A SN74LV138A

MIN TYP MAX MIN MAX MIN MAX

5.7 8.1 1 9.5 1 9.5

7.1 10.1 1 11.5 1 11.5

operating characteristics, TA = 25°C

PARAMETER TEST CONDITIONS V

p

p

p

p

= 50 F,f = 10

CC

3.3 V 16.8
5 V 19.1

ns

ns

TYP UNIT

p

PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5

SN54LV138A, SN74LV138A
3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS

SCLS395B – APRIL 1998 – REVISED JUL Y 1998

PARAMETER MEASUREMENT INFORMATION

From Output

Under Test

(see Note A)

Test
Point

C

L

From Output

Under Test

(see Note A)

C

L

RL = 1 kΩ

S1

V

CC

GND

Open

TEST S1

t

PLH/tPHL

t

PLZ/tPZL

t

PHZ/tPZH

Open Drain

Open

V

CC

GND
V

CC

LOAD CIRCUIT FOR

TOTEM-POLE OUTPUTS

t

w

Input

Input

In-Phase

Output

Out-of-Phase

Output

INVERTING AND NONINVERTING OUTPUTS

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.

E. t
F. t

G. t

50% V

CC

VOLTAGE WAVEFORMS

PULSE DURATION

50% V

CC

t

PLH

50% V

CC

t

PHL

50% V

CC

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

PLZ
PZL
PHL

and t
and t

and t

are the same as t

PHZ

are the same as ten.

PZH

are the same as tpd.

PLH

3-STATE AND OPEN-DRAIN OUTPUTS

50% V

50% V

dis

CC

t

PHL

50% V

t

PLH

50% V

.

LOAD CIRCUIT FOR

V

CC

CC

0 V

V

CC

0 V

V

OH

CC

V

OL

V

OH

CC

V

OL

Timing Input

Data Input

Output

Control

Output

Waveform 1

S1 at V

(see Note B)

Waveform 2

(see Note B)

CC

Output

S1 at GND

50% V

CC

t

CC

CC

h

50% V

50% V

VOL + 0.3 V

VOH – 0.3 V

CC

CC

t

su

50% V

CC

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

50% V

CC

t

PZL

t

PZH

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

LOW- AND HIGH-LEVEL ENABLING

t

PLZ

50% V

t

PHZ

50% V

V

CC

0 V

V

CC

0 V

V

CC

0 V

≈ V

V

OL

V

OH

≈ 0 V

CC

Figure 1. Load Circuit and Voltage Waveforms

6

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Copyright  1998, Texas Instruments Incorporated