Datasheet SN74LV125AD, SN74LV125ADBLE, SN74LV125ADBR, SN74LV125ADGVR, SN74LV125ADR Datasheet (Texas Instruments)

SN54LV125A, SN74LV125A

QUADRUPLE BUS BUFFER GATES

WITH 3-STATE OUTPUTS

SCES124D – DECEMBER 1997 – REVISED JUL Y 1998

D

EPIC

 (Enhanced-Performance Implanted

CMOS) Process

D

Typical V
< 0.8 V at V

D

Typical V
> 2 V at V

D

Latch-Up Performance Exceeds 250 mA Per

(Output Ground Bounce)

OLP

, TA = 25°C

CC

(Output VOH Undershoot)

OHV

, TA = 25°C

CC

JESD 17

D

ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)

D

Package Options Include Plastic
Small-Outline (D, NS), Shrink Small-Outline
(DB), Thin Very Small-Outline (DGV), and
Thin Shrink Small-Outline (PW) Packages,
Ceramic Flat (W) Packages, Chip Carriers
(FK), and DIPs (J)

description

The ‘LV125A quadruple bus buffer gates are
designed for 2-V to 5.5-V V

These devices feature independent line drivers
with 3-state outputs. Each output is disabled when
the associated output-enable (OE

T o ensure the high-impedance state during power
up or power down, OE
through a pullup resistor; the minimum value of
the resistor is determined by the current-sinking
capability of the driver.

operation.

CC

) input is high.

should be tied to V

CC

SN74LV125A. . . D, DB, DGV, NS, OR PW PACKAGE

SN54LV125A...J OR W PACKAGE

(TOP VIEW)

NC

NC

14
13
12
11
10

V

CC

4OE
4A
4Y
3OE

9

3A

8

3Y

CC

V

4OE

4A

18

NC

17

4Y

16

NC

15
14

3OE

3Y

3A

1OE

1

1A

2

1Y

3

2OE

4

2A

5
6

2Y

GND

SN54LV125A. . . FK PACKAGE

1Y

NC

2OE

NC

2A

NC – No internal connection

7

(TOP VIEW)

1A

1OE

3212019

4
5
6
7
8

910111213

2Y

GND

The SN54L V125A is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74LV125A is characterized for operation from –40°C to 85°C.

FUNCTION TABLE

(each buffer)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC is a trademark of Texas Instruments Incorporated.

UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.

INPUTS

OE

L H H
L LL

HXZ

OUTPUT

A

Y

Copyright  1998, Texas Instruments Incorporated

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

1

SN54LV125A, SN74LV125A
QUADRUPLE BUS BUFFER GATES
WITH 3-STATE OUTPUTS

SCES124D – DECEMBER 1997 – REVISED JUL Y 1998

logic symbol

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

Pin numbers shown are for the D, DB, DGV, J, NS, PW, and W packages.

†

1OE

1A

2OE

2A

3OE

3A

4OE

4A

1
2
4
5

10
9

13
12

EN

1

logic diagram (positive logic)

1

1OE

2

1A 1Y

4

2OE

5

2A 2Y

3

6

3OE

3A 3Y

4OE

4A 4Y

10

9

13

12

3

1Y

6

2Y

8

3Y

11

4Y

8

11

Pin numbers shown are for the D, DB, DGV, J, NS, PW, and W packages.

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V
Input voltage range, V
Output voltage range, V
Input clamp current, I
Output clamp current, I
Continuous output current, I
Continuous current through V
Package thermal impedance, θ

Operating free-air temperature range, T
Storage temperature range, T

‡

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

2. This value is limited to 7 V maximum.

3. The package thermal impedance is calculated in accordance with JESD 51.

–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC

(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I

(see Notes 1 and 2) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

O

(VI < 0) –20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

IK

(VO < 0 or VO > VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

OK

(VO = 0 to VCC) ±35 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

O

or GND ±70 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC

(see Note 3): D package 127°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

JA

DB package 158°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DGV package 182°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

NS package 127°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PW package 170°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

A

‡

2

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UNIT

VIHHigh-level input voltage

V

VILLow-level input voltage

V

VOOutput voltage

V

IOHHigh-level output current

IOLLow-level output current

PARAMETER

TEST CONDITIONS

V

UNIT

V

V

V

V

SN54LV125A, SN74LV125A

QUADRUPLE BUS BUFFER GATES

WITH 3-STATE OUTPUTS

SCES124D – DECEMBER 1997 – REVISED JUL Y 1998

recommended operating conditions (see Note 4)

SN54LV125A SN74LV125A

MIN MAX MIN MAX

V

V

∆t/∆v Input transition rise or fall rate

T

NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,

Supply voltage 2 5.5 2 5.5 V

CC

VCC = 2 V 1.5 1.5

p

p

Input voltage 0 5.5 0 5.5 V

I

p

p

p

Operating free-air temperature –55 125 –40 85 °C

A

Implications of Slow or Floating CMOS Inputs

VCC = 2.3 V to 2.7 V VCC × 0.7 VCC × 0.7
VCC = 3 V to 3.6 V VCC × 0.7 VCC × 0.7
VCC = 4.5 V to 5.5 V VCC × 0.7 VCC × 0.7
VCC = 2 V 0.5 0.5
VCC = 2.3 V to 2.7 V VCC × 0.3 VCC × 0.3
VCC = 3 V to 3.6 V VCC × 0.3 VCC × 0.3
VCC = 4.5 V to 5.5 V VCC × 0.3 VCC × 0.3

High or low state 0 V
3-state 0 5.5 0 5.5
VCC = 2 V –50 –50 µ A
VCC = 2.3 V to 2.7 V –2 –2
VCC = 3 V to 3.6 V –8 –8
VCC = 4.5 V to 5.5 V –16 –16
VCC = 2 V 50 50 µA
VCC = 2.3 V to 2.7 V 2 2
VCC = 3 V to 3.6 V 8 8
VCC = 4.5 V to 5.5 V 16 16
VCC = 2.3 V to 2.7 V 0 200 0 200
VCC = 3 V to 3.6 V 0 100 0 100
VCC = 4.5 V to 5.5 V 0 20 0 20

, literature number SCBA004.

CC

0 V

CC

mA

mA

ns/V

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)

PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.

I
I
I
I
C

OH

OL

I
OZ
CC
off

i

CC

IOH = –50 µA 2 V to 5.5 V VCC–0.1 VCC–0.1
IOH = –2 mA 2.3 V 2 2
IOH = –8 mA 3 V 2.48 2.48
IOH = –16 mA 4.5 V 3.8 3.8
IOL = 50 µA 2 V to 5.5 V 0.1 0.1
IOL = 2 mA 2.3 V 0.4 0.4
IOL = 8 mA 3 V 0.44 0.44
IOL = 16 mA 4.5 V 0.55 0.55
VI = VCC or GND 5.5 V ±1 ±1 µA
VO = VCC or GND 5.5 V ±5 ±5 µA
VI = VCC or GND, IO = 0 5.5 V 20 20 µA
VI or VO = 0 to 5.5 V 0 V 5 5 µA
VI = VCC or GND 3.3 V 2 2 pF

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SN54LV125A SN74LV125A

MIN TYP MAX MIN TYP MAX

3

SN54LV125A, SN74LV125A

PARAMETER

UNIT

C

pF

ns

PARAMETER

UNIT

C

pF

ns

PARAMETER

UNIT

C

pF

ns

QUADRUPLE BUS BUFFER GATES
WITH 3-STATE OUTPUTS

SCES124D – DECEMBER 1997 – REVISED JUL Y 1998

switching characteristics over recommended operating free-air temperature range,

= 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1)

V

CC

FROM TO LOAD

(INPUT) (OUTPUT) CAPACITANCE

tpd*
ten* OE Y
t

* OE Y 5.1 14.7 1 17 1 17

dis

t

pd

t

en

t

dis

†

t

sk(o)

* On products compliant to MIL-PRF-38535, this parameter is not production tested.
†

Skew between any two outputs of the same package switching in the same direction

A Y 6.8 13 1 15.5 1 15.5

CL = 15 pF

A Y 8.7 16.5 1 18.5 1 18.5
OE Y
OE Y

= 50

L

p

switching characteristics over recommended operating free-air temperature range,

= 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)

V

CC

FROM TO LOAD

(INPUT) (OUTPUT) CAPACITANCE

tpd*
ten* OE Y
t

* OE Y 4.1 9.7 1 11.5 1 11.5

dis

t

pd

t

en

t

dis

†

t

sk(o)

* On products compliant to MIL-PRF-38535, this parameter is not production tested.
†

Skew between any two outputs of the same package switching in the same direction

A Y 4.8 8 1 9.5 1 9.5

CL = 15 pF

A Y 6.1 11.5 1 13 1 13
OE Y
OE Y

= 50

L

p

TA = 25°C SN54LV125A SN74LV125A

MIN TYP MAX MIN MAX MIN MAX

7 13 1 15.5 1 15.5

8.8 16.5 1 18.5 1 18.5

7.3 18.2 1 20.5 1 20.5
2 2

TA = 25°C SN54LV125A SN74LV125A

MIN TYP MAX MIN MAX MIN MAX

4.8 8 1 9.5 1 9.5

6.2 11.5 1 13 1 13

5.5 13.2 1 15 1 15

1.5 1.5

ns

ns

switching characteristics over recommended operating free-air temperature range,

= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)

V

CC

FROM TO LOAD

(INPUT) (OUTPUT) CAPACITANCE

tpd*
ten* OE Y
t

* OE Y 3.2 6.8 1 8 1 8

dis

t

pd

t

en

t

dis

†

t

sk(o)

* On products compliant to MIL-PRF-38535, this parameter is not production tested.
†

Skew between any two outputs of the same package switching in the same direction

PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.

A Y 3.4 5.5 1 6.5 1 6.5

CL = 15 pF

A Y 4.3 7.5 1 8.5 1 8.5
OE Y
OE Y

= 50

L

p

TA = 25°C SN54LV125A SN74LV125A

MIN TYP MAX MIN MAX MIN MAX

3.4 5.1 1 6 1 6

4.4 7.1 1 8 1 8
4 8.8 1 10 1 10

1 1

ns

4

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PARAMETER

UNIT

C

d

Power dissipation capacitance

Outputs enabled

C

pF

QUADRUPLE BUS BUFFER GATES

SCES124D – DECEMBER 1997 – REVISED JUL Y 1998

noise characteristics, VCC = 3.3 V, CL = 50 pF, TA = 25°C (see Note 5)

V

OL(P)

V

OL(V)

V

OH(V)

V

IH(D)

V

IL(D)

NOTE 5: Characteristics are for surface-mount packages only.

Quiet output, maximum dynamic V
Quiet output, minimum dynamic V
Quiet output, minimum dynamic V
High-level dynamic input voltage 2.31 V
Low-level dynamic input voltage 0.99 V

OL
OL
OH

SN54LV125A, SN74LV125A

WITH 3-STATE OUTPUTS

SN74LV125A

MIN TYP MAX

0.36 0.8 V

–0.27 –0.8 V

3.04 V

operating characteristics, T

PARAMETER

p

p

p

= 25°C

A

TEST CONDITIONS V

p

p

= 50 pF,f = 10 MHz

L

3.3 V 15.5

TYP UNIT

CC

5 V 17.6

p

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5

SN54LV125A, SN74LV125A
QUADRUPLE BUS BUFFER GATES
WITH 3-STATE OUTPUTS

SCES124D – DECEMBER 1997 – REVISED JUL Y 1998

PARAMETER MEASUREMENT INFORMATION

From Output

Under Test

(see Note A)

Test
Point

C

L

From Output

Under Test

(see Note A)

V

RL = 1 kΩ

C

L

S1

CC

Open

GND

TEST S1

t

PLH/tPHL

t

PLZ/tPZL

t

PHZ/tPZH

Open Drain

Open

V

CC

GND
V

CC

LOAD CIRCUIT FOR

TOTEM-POLE OUTPUTS

t

w

Input

Input

In-Phase

Output

Out-of-Phase

Output

INVERTING AND NONINVERTING OUTPUTS

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
E. t
F. t

G. t

50% V

CC

VOLTAGE WAVEFORMS

PULSE DURATION

50% V

CC

t

PLH

50% V

CC

t

PHL

50% V

CC

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

PLZ
PZL
PHL

and t
and t

and t

are the same as t

PHZ

are the same as ten.

PZH

are the same as tpd.

PLH

3-STATE AND OPEN-DRAIN OUTPUTS

50% V

50% V

dis

CC

t

PHL

50% V

t

PLH

50% V

.

LOAD CIRCUIT FOR

V

CC

CC

0 V

V

CC

0 V

V

OH

CC

V

OL

V

OH

CC

V

OL

Timing Input

Data Input

Output

Control

Output

Waveform 1

S1 at V

(see Note B)

Waveform 2

(see Note B)

CC

Output

S1 at GND

50% V

CC

t

CC

CC

h

50% V

50% V

CC

CC

VOL + 0.3 V

VOH – 0.3 V

t

su

50% V

CC

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

50% V

CC

t

PZL

t

PZH

VOLTAGE WA VEFORMS

ENABLE AND DISABLE TIMES

LOW- AND HIGH-LEVEL ENABLING

t

PLZ

50% V

t

PHZ

50% V

V

CC

0 V

V

CC

0 V

V

CC

0 V

≈ V

V

OL

V

OH

≈ 0 V

CC

Figure 1. Load Circuit and Voltage Waveforms

6

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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
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Copyright  1998, Texas Instruments Incorporated