Datasheet SN74LS74AM, SN74LS74AMEL, SN74LS74AML1, SN74LS74AML2, SN74LS74AMR1 Datasheet (MOTOROLA)

 Semiconductor Components Industries, LLC, 1999

December, 1999 – Rev. 6

1 Publication Order Number:

SN74LS74A/D

SN74LS74A

Dual D-Type Positive
Edge-Trigger ed Flip-Flop

The SN74LS74A dual edge-triggered flip-flop utilizes Schottky
TTL circuitry to produce high speed D-type flip-flops. Each flip-flop
has individual clear and set inputs, and also complementary Q and Q
outputs.

Information at input D is transferred to the Q output on the
positive-going edge of the clock pulse. Clock triggering occurs at a
voltage level of the clock pulse and is not directly related to the
transition time of the positive-going pulse. When the clock input is at
either the HIGH or the LOW level, the D input signal has no effect.

MODE SELECT – TRUTH TABLE

INPUTS OUTPUTS

OPERATING MODE

S

D

S

D

D Q Q

Set
Reset (Clear)
*Undetermined
Load “1” (Set)
Load “0” (Reset)

L
H
L
H
H

H
L
L
H
H

X
X
X
h

l

H
L
H
H
L

L
H
H
L
H

* Both outputs will be HIGH while both SD and CD are LOW, but the output

states are unpredictable if S

D

and CD go HIGH simultaneously. If the levels

at the set and clear are near V

IL

maximum then we cannot guarantee to meet

the minimum level for V

OH

.
H, h = HIGH Voltage Level
L, I = LOW Voltage Level
X = Don’t Care
l, h (q) = Lower case letters indicate the state of the referenced input

i, h (q) = (or output) one set-up time prior to the HIGH to LOW clock transition.

GUARANTEED OPERATING RANGES

Symbol Parameter Min Typ Max Unit

V

CC

Supply Voltage 4.75 5.0 5.25 V

T

A

Operating Ambient

T emperature Range

0 25 70 °C

I

OH

Output Current – High –0.4 mA

I

OL

Output Current – Low 8.0 mA

LOW

POWER

SCHOTTKY

Device Package Shipping

ORDERING INFORMATION

SN74LS74AN 14 Pin DIP 2000 Units/Box
SN74LS74AD 14 Pin

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LOGIC DIAGRAM (Each Flip-Flop)

LOGIC SYMBOL

SET (SD)

4 (10)

CLEAR (CD

)
1 (13)

CLOCK

3 (11)

D

2 (12)

Q

5 (9)

Q

6 (8)

VCC = PIN 14
GND = PIN 7

2
3

5

DQ

CP

Q

C

D

1

4

6

12
11

9

DQ

CP

Q

C

D

13

10

8

S

D

S

D

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DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)

Limits

Symbol Parameter

Min Typ Max

Unit Test Conditions

V

IH

Input HIGH Voltage 2.0 V

Guaranteed Input HIGH Voltage for
All Inputs

V

IL

Input LOW Voltage

0.8
V

Guaranteed Input LOW Voltage for
All Inputs

V

IK

Input Clamp Diode Voltage –0.65 –1.5 V VCC = MIN, IIN = –18 mA

V

OH

Output HIGH Voltage

2.7 3.5 V VCC = MIN, IOH = MAX, VIN = V

IH

or VIL per Truth Table

p

0.25 0.4 V IOL = 4.0 mA

VCC = VCC MIN,

VOLOutput LOW Voltage

0.35 0.5 V IOL = 8.0 mA

V

IN

=

V

IL

or

V

IH

per Truth Table

I

IH

Input High Current

Data, Clock
Set, Clear

20
40

µA VCC = MAX, VIN = 2.7 V

IH

Data, Clock
Set, Clear

0.1

0.2

mA VCC = MAX, VIN = 7.0 V

I

IL

Input LOW Current

Data, Clock
Set, Clear

–0.4
–0.8

mA VCC = MAX, VIN = 0.4 V

I

OS

Output Short Circuit Current (Note 1) –20 –100 mA VCC = MAX

I

CC

Power Supply Current 8.0 mA VCC = MAX

Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.

AC CHARACTERISTICS (T

A

= 25°C, VCC = 5.0 V)

Limits

Symbol Parameter

Min Typ Max

Unit Test Conditions

f

MAX

Maximum Clock Frequency 25 33 MHz Figure 1

t

PLH

p

13 25 ns

VCC = 5.0 V

=

p

PLH

t

PHL

Clock, Clear, Set to Output

25 40 ns

Figure 1

C

L

= 15

F

AC SETUP REQUIREMENTS (T

A

= 25°C)

Limits

Symbol Parameter

Min Typ Max

Unit Test Conditions

t

W(H)

Clock 25 ns Figure 1

t

W(L)

Clear, Set 25 ns Figure 2
Data Setup Time — HIGH

20 ns

VCC = 5.0 V

t

s

Data Setup Time — LOW

20 ns

Figure 1

t

h

Hold Time 5.0 ns Figure 1

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Figure 1. Clock to Output Delays, Data

Set-Up and Hold Times, Clock Pulse Width

AC WAVEFORMS

*The shaded areas indicate when the input is permitted to change for predictable output performance.

D*

CP

Q

Q

1.3 V 1.3 V

1.3 V1.3 V

1.3 V

1.3 V

1.3 V

t

PLH

t

PHL

t

PLH

t

PHL

t

h(L)

t

s(L)

t

W(H)

t

W(L)

t

s(H)

t

h(H)

1

f

MAX

1.3 V

Figure 2. Set and Clear to Output Delays,

Set and Clear Pulse Widths

t

W

1.3 V 1.3 V

t

W

1.3 V 1.3 V

1.3 V

1.3 V1.3 V

1.3 V

t

PLH

t

PHL

t

PLH

t

PHL

SET

CLEAR

Q

Q

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P ACKAGE DIMENSIONS

17

14 8

B

A

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A 0.715 0.770 18.16 18.80
B 0.240 0.260 6.10 6.60
C 0.145 0.185 3.69 4.69
D 0.015 0.021 0.38 0.53
F 0.040 0.070 1.02 1.78
G 0.100 BSC 2.54 BSC
H 0.052 0.095 1.32 2.41
J 0.008 0.015 0.20 0.38
K 0.115 0.135 2.92 3.43
L
M ––– 10 ––– 10
N 0.015 0.039 0.38 1.01

__

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

F

HG

D

K

C

SEATING
PLANE

N

–T–

14 PL

M

0.13 (0.005)

L

M

J

0.290 0.310 7.37 7.87

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P ACKAGE DIMENSIONS

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.

–A–

–B–

G

P

7 PL

14 8

71

M

0.25 (0.010) B

M

S

B

M

0.25 (0.010) A

S

T

–T–

F

R

X 45

SEATING
PLANE

D 14 PL

K

C

J

M

_

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A 8.55 8.75 0.337 0.344
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
F 0.40 1.25 0.016 0.049
G 1.27 BSC 0.050 BSC
J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009
M 0 7 0 7
P 5.80 6.20 0.228 0.244
R 0.25 0.50 0.010 0.019

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Notes

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