Page 1
DUAL JK NEGATIVE
OPERATING MODE
EDGE-TRIGGERED FLIP-FLOP
The SN54LS/74LS73A offers individual J, K, clear , and clock inputs. These
dual flip-flops are designed so that when the clock goes HIGH, the inputs are
enabled and data will be accepted. The logic level of the J and K inputs may
be allowed to change when the clock pulse is HIGH and the bistable will perform according to the truth table as long as minimum set-up times are observed. Input data is transferred to the outputs on the negative-going edge of
the clock pulse.
SN54/74LS73A
DUAL JK NEGATIVE
EDGE-TRIGGERED FLIP-FLOP
LOW POWER SCHOTTKY
LOGIC DIAGRAM (Each Flip-Flop)
Q
13 (8)
K
3 (10)
1 (15)
CLOCK (CP)
Q
12 (9)
CLEAR
2 (6)
J
14 (7)
MODE SELECT — TRUTH TABLE
INPUTS OUTPUTS
C
D
Reset (Clear)
Toggle
Load “0” (Reset)
Load “1” (Set)
Hold
H, h = HIGH Voltage Level
L, I = LOW Voltage Level
X = Don’t Care
l, h (q) = Lower case letters indicate the state of the referenced input (or output) one set-up time
l, h (q) = prior to the HIGH to LOW clock transition.
L
H
H
H
H
J K Q Q
X
h
l
h
l
X
h
h
l
l
L
q
L
H
q
H
q
H
L
q
14
1
14
1
14
1
ORDERING INFORMATION
SN54LSXXJ Ceramic
SN74LSXXN Plastic
SN74LSXXD SOIC
LOGIC SYMBOL
D
VCC = PIN 4
GND = PIN 11
12
13
10
14
JQ
1
CP
3
KQ
C
2
J SUFFIX
CERAMIC
CASE 632-08
N SUFFIX
PLASTIC
CASE 646-06
D SUFFIX
SOIC
CASE 751A-02
7
JQ
5
CP
KQ
C
D
6
9
8
FAST AND LS TTL DAT A
5-1
Page 2
SN54/74LS73A
VILI
LOW Volt
V
pg
VOHOutput HIGH Volt
CC
,
OH
,
IN IH
VOLOutput LOW Volt
V
V
V
IIHI
HIGH C
t
PLH
pg y,
Fi
1
C
L
pF
V
5.0 V
Fi
1
GUARANTEED OPERATING RANGES
Symbol Parameter Min Typ Max Unit
V
CC
T
A
I
OH
I
OL
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Symbol Parameter
V
IH
V
IK
I
IL
I
OS
I
CC
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS (T
Symbol Parameter
f
MAX
t
PLH
t
PHL
Supply Voltage 54
Operating Ambient Temperature Range 54
Output Current — High 54, 74 –0.4 mA
Output Current — Low 54
Min Typ Max
Input HIGH Voltage 2.0 V
nput
Input Clamp Diode Voltage –0.65 –1.5 V VCC = MIN, IIN = –18 mA
nput
Input LOW Current
Short Circuit Current (Note 1) –20 –100 mA VCC = MAX
Power Supply Current 6.0 mA VCC = MAX
Maximum Clock Frequency 30 45 MHz Figure 1
Propagation Delay,
Clock to Output
age
age
age
urren
= 25°C, VCC = 5.0 V)
A
54 0.7
74 0.8
54 2.5 3.5 V
74 2.7 3.5 V
54, 74 0.25 0.4 V IOL = 4.0 mA
74 0.35 0.5 V IOL = 8.0 mA
J, K
Clear
Clock
J, K
Clear
Clock
J, K
Clear, Clock
Min Typ Max
74
74
74
Limits
–0.4
–0.8
Limits
15 20 ns
15 20 ns
4.5
4.75
–55
0
Unit Test Conditions
20
60
80
0.1
0.3
0.4
µA VCC = MAX, VIN = 2.7 V
mA VCC = MAX, VIN = 7.0 V
mA VCC = MAX, VIN = 0.4 V
Unit Test Conditions
5.0
5.0
25
25
Guaranteed Input HIGH Voltage for
All Inputs
Guaranteed Input LOW Voltage for
All Inputs
VCC = MIN, IOH = MAX, VIN = V
or VIL per Truth Table
gure
5.5
5.25
125
70
4.0
8.0
VCC = VCC MIN,
=
IN
per Truth Table
VCC = 5.0 V
C
= 15 pF
= 15
V
°C
mA
IH
or
IL
IH
AC SETUP REQUIREMENTS (T
Symbol Parameter
t
W
t
W
t
s
t
h
= 25°C)
A
Limits
Min Typ Max
Clock Pulse Width High 20 ns Figure 1
Clear Pulse Width 25 ns Figure 2
Setup Time 20 ns
Hold Time 0 ns
FAST AND LS TTL DATA
5-2
Unit Test Conditions
CC
gure
=
Page 3
SN54/74LS73A
AC WAVEFORMS
J or K *
t
=0
t
s(L)
CP
Q
Q
*The shaded areas indicate when the input is permitted to change for predictable output performance.
1.3 V
h(L)
t
W(L)
1.3 V 1.3 V
1
f
t
PHL
1.3 V 1.3 V
t
PLH
1.3 V
MAX
t
W(H)
1.3 V
t
s(H)
t
PLH
t
PHL
t
h(H)
=0
1.3 V
Figure 1. Clock to Output Delays, Data
Set-Up and Hold Times, Clock Pulse Width
SET
CLEAR
Q
Q
t
W
1.3 V 1.3 V
1.3 V 1.3 V
t
PLH
1.3 V
t
PHL
Figure 2. Set and Clear to Output Delays,
Set and Clear Pulse Widths
t
W
t
PHL
1.3 V
t
PLH
1.3 V1.3 V
FAST AND LS TTL DATA
5-3
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