
4 x 4 REGISTER FILE
WITH 3-STATE OUTPUTS
The TTL/MSI SN54/74LS670 is a high-speed, low-power 4 x 4 Register
File organized as four words by four bits. Separate read and write inputs, both
address and enable, allow simultaneous read and write operation.
The 3-state outputs make it possible to connect up to 128 outputs to increase the word capacity up to 512 words. Any number of these devices can
be operated in parallel to generate an n-bit length.
The SN54/74LS170 provides a similar function to this device but it features
open-collector outputs.
• Simultaneous Read/Write Operation
• Expandable to 512 Words by n-Bits
• Typical Access Time to 20 ns
• 3-State Outputs for Expansion
• Typical Power Dissipation of 125 mW
SN54/74LS670
4 x 4 REGISTER FILE
WITH 3-STATE OUTPUTS
LOW POWER SCHOTTKY
J SUFFIX
CERAMIC
16
1
CASE 620-09
CONNECTION DIAGRAM DIP (TOP VIEW)
Q
V
D1WAWBE
CC
16 15
123456
D
2
PIN NAMES LOADING (Note a)
D1 – D
4
WA, W
B
E
W
RA, R
B
E
R
Q1 – Q
4
NOTES:
a) 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.
b) The Output LOW drive factor is 7.5 U.L. for Military (54) and 15 U.L. for Commercial
(74) T emperature Ranges. The Output HIGH drive factor is 25 U.L. for Military and
65 U.L. for Commercial Temperature Ranges.
14 13 12 11 10 9
D3D4RBRAQ4Q3GND
Data Inputs 0.5 U.L. 0.25 U.L.
Write Address Inputs 0.5 U.L. 0.25 U.L.
Write Enable (Active LOW) Input 1.0 U.L. 0.5 U.L.
Read Address Inputs 0.5 U.L. 0.25 U.L.
Read Enable (Active LOW) Input 1.5 U.L. 0.75 U.L.
Outputs (Note b) 65 (25) U.L. 15 (7.5) U.L.
E
W
R
Q
1
7
2
NOTE:
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual In-Line Package.
8
HIGH
LOW
N SUFFIX
16
1
16
1
CASE 648-08
D SUFFIX
CASE 751B-03
ORDERING INFORMATION
SN54LSXXXJ Ceramic
SN74LSXXXN Plastic
SN74LSXXXD SOIC
LOGIC SYMBOL
12 15 1 2 3
14
13
E
W
A
W
B
5
R
A
R
4
E
B
D
W
1
Q1Q2Q3Q
R
D
D3D
2
PLASTIC
SOIC
4
4
FAST AND LS TTL DAT A
5-1
11 10 9 7 6
VCC = PIN 16
GND = PIN 8

SN54/74LS670
GUARANTEED OPERATING RANGES
Symbol Parameter Min Typ Max Unit
V
CC
T
A
I
OH
I
OL
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Symbol Parameter
V
IH
V
IK
I
OZH
I
OZL
I
IH
I
IL
I
OS
I
CC
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
Supply Voltage 54
Operating Ambient Temperature Range 54
Output Current — High 54
Output Current — Low 54
Limits
Min Typ Max
Input HIGH Voltage 2.0 V
nput
Input Clamp Diode Voltage –0.65 –1.5 V VCC = MIN, IIN = –18 mA
Output Off Current HIGH 20 µA VCC = MAX, VO = 2.7 V
Output Off Current LOW –20 µA VCC = MAX, VO = 0.4 V
Input HIGH Current
D, R, W
E
W
E
R
D, R, W
E
W
E
R
Input LOW Current
D, R, W
E
W
E
R
Short Circuit Current (Note 1) –30 –130 mA VCC = MAX
Power Supply Current 50 mA VCC = MAX
age
age
age
54
74
54 2.4 3.4 V
74 2.4 3.1 V
54, 74 0.25 0.4 V IOL = 12 mA
74 0.35 0.5 V IOL = 24 mA
74
74
74
74
0.7
0.8
20
40
60
0.1
0.2
0.3
–0.4
–0.8
–1.2
4.5
4.75
–55
0
Unit Test Conditions
Guaranteed Input HIGH Voltage for
All Inputs
Guaranteed Input LOW Voltage for
All Inputs
VCC = MIN, IOH = MAX, VIN = V
or VIL per Truth Table
µA VCC = MAX, VIN = 2.7 V
mA VCC = MAX, VIN = 7.0 V
mA VCC = MAX, VIN = 0.4 V
5.0
5.0
25
25
5.5
5.25
125
70
–1.0
–2.6
12
24
IH
VCC = VCC MIN,
=
or
IN
IL
per Truth Table
IH
V
°C
mA
mA
FAST AND LS TTL DATA
5-3

SN54/74LS670
AC CHARACTERISTICS (T
Symbol Parameter
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PLZ
t
PHZ
Propagation Delay, RA or R
to Output
Propagation Delay, EW to
Output
Propagation Delay, Data
to Output
Output Enable Time
Output Disable Time
= 25°C)
A
AC SETUP REQUIREMENTS (T
Symbol Parameter
t
t
t
t
t
t
W
s
s
h
h
rec
Pulse Width 25 ns
Setup Time, (D) 10 ns
Setup Time, (W) 15 ns
Hold Time, (D) 15 ns
Hold Time, (W) 5.0 ns
Recovery Time 25 ns
= 25°C)
A
Limits
Min Typ Max
B
Min Typ Max
23
25
26
28
25
23
15
22
16
30
Limits
Unit Test Conditions
40
45
45
50
45
40
35
40
35
50
ns
ns
ns
ns
ns CL = 5.0 pF
Unit Test Conditions
VCC = 5.0 V,
CL = 45 pF
= 5.0
CC
D, E
AC WAVEFORMS
W
1.3 V 1.3 V 1.3 V 1.3 V
t
PHL
1.3 V
t
PLH
1.3 V
Figure 1
WA, W
E
W
B
D
1.3 V 1.3 V
t
s
RA, R
B
t
PHL
QQ
1.3 V
t
PLH
1.3 V
Figure 2
t
h
1.3 V1.3 V
t
t
s
t
W
h
1.3 V1.3 V
Figure 3
FAST AND LS TTL DATA
5-4