Page 1
DUAL DECADE COUNTER
The SN54/74LS490 contains a pair of high-speed 4-stage ripple counters.
Each half of the SN54/74LS490 has individual Clock, Master Reset and Master Set (Preset 9) inputs. Each section counts in the 8, 4, 2, 1 BCD code.
SN54/74LS490
• Dual Version of SN54/74LS490
• Individual Asynchronous Clear and Preset to 9 for Each Counter
• Count Frequency — Typically 65 MHz
• Input Clamp Diodes Limit High-Speed Termination Effects
CONNECTION DIAGRAM DIP (TOP VIEW)
CP
V
CP
PIN NAMES LOADING (Note a)
MS Master Set (Set to 9) Input 0.5 U.L. 0.25 U.L.
MR Master Reset 0.5 U.L. 0.25 U.L.
CP Clock Input (Active LOW Going Edge) 1.5 U.L. 1.5 U.L.
Q0–Q3Counter Outputs (Note b) 10 U.L. 5 (2.5) U.L.
NOTES:
a) 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.
b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial
(74) T emperature Ranges.
bMRbQ0bMSb
CC
16 15
123456
a
14 13 12 11 10 9
MRaQ0aMSaQ1aQ2aQ3aGND
Q
Q
1b
Q
2b
7
HIGH
3b
8
LOW
DUAL DECADE COUNTER
LOW POWER SCHOTTKY
J SUFFIX
CERAMIC
16
1
16
1
16
1
ORDERING INFORMATION
SN54LSXXXJ Ceramic
SN74LSXXXN Plastic
SN74LSXXXD SOIC
CASE 620-09
N SUFFIX
PLASTIC
CASE 648-08
D SUFFIX
SOIC
CASE 751B-03
LOGIC DIAGRAM (ONE HALF SHOWN)
15
4
12
1
K
14
J
C
S
D
D
Q
2
3 Q0 13 5 Q1 11 6 Q2 10 7 Q3 9
K
J
C
D
Q
MS
CP
MR
K
J
C
D
Q
CP
K
C
D
FAST AND LS TTL DATA
5-1
TRUTH TABLE
OUTPUTS
COUNT Q
0 L L L L
1 L L L H
2 L L H L
J
S
D
Q
3 L L H H
4 L H L L
5 L H L H
6 L H H L
7 L H H H
8 H L L L
9 H L L H
Q
Q
3
2
Q
1
0
Page 2
SN54/74LS490
VILI
LOW Volt
V
pg
VOHOutput HIGH Volt
CC
,
OH
,
IN IH
VOLOutput LOW Volt
V
V
V
IIHI
HIGH C
t
IILI
LOW C
t
A
V
MAX, V
V
V
V
GUARANTEED OPERATING RANGES
Symbol Parameter Min Typ Max Unit
V
CC
T
A
I
OH
I
OL
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Symbol Parameter
V
IH
V
IK
I
OS
I
CC
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
Supply Voltage 54
Operating Ambient Temperature Range 54
Output Current — High 54, 74 –0.4 mA
Output Current — Low 54
Limits
Min Typ Max
Input HIGH Voltage 2.0 V
nput
Input Clamp Diode Voltage –0.65 –1.5 V VCC = MIN, IIN = –18 mA
nput
nput
Short Circuit Current (Note 1) –20 –100 mA VCC = MAX
Power Supply Current 26 mA VCC = MAX
age
age
age
urren
urren
54
74
54 2.5 3.5 V
74 2.7 3.5 V
54, 74 0.25 0.4 V IOL = 4.0 mA
74 0.35 0.5 V IOL = 8.0 mA
MS, MR –0.4
Clock –1.6
74
74
74
0.7
0.8
20 µA VCC = MAX, VIN = 2.7 V
0.1 mA VCC = MAX, VIN = 7.0 V
4.5
4.75
–55
0
Unit Test Conditions
Guaranteed Input HIGH Voltage for
All Inputs
Guaranteed Input LOW Voltage for
All Inputs
VCC = MIN, IOH = MAX, VIN = V
or VIL per Truth Table
m
CC
=
5.0
5.0
25
25
5.5
5.25
125
70
4.0
8.0
VCC = VCC MIN,
=
IN
per Truth Table
= 0.4
IN
IL
IH
or
V
°C
mA
IH
AC SET-UP REQUIREMENTS (T
t
W
t
s
A
Symbol Parameter
Any Pulse Width 20 ns
MR or MS to Setup Time 25 ns
= 25°C, VCC = 5.0 V)
Min Typ Max
FAST AND LS TTL DATA
Limits
5-2
Unit Test Conditions
= 5.0
CC
Page 3
SN54/74LS490
CC
,
AC CHARACTERISTICS (T
Symbol Parameter
f
MAX
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PHL
t
PLH
t
PHL
Maximum Clock Frequency 25 35 MHz Figure 1
Propagation Delay, CP to Q
Propagation Delay, CP to Q1 or Q
Propagation Delay, CP to Q
Propagation Delay, MR to Output 24 39 ns Figure 2
Propagation Delay, MS to Output
= 25°C)
A
*CP
Q
Limits
Min Typ Max
0
3
2
12
13
24
26
32
36
24
20
AC WAVEFORMS
1.3 V 1.3 V
t
PHL
Figure 1
Unit Test Conditions
20
20
39
39
54
54
39
36
t
W
ns Figure 1
ns Figure 3
ns Figure 2
ns Figure 2
t
PLH
1.3 V1.3 V
VCC = 5.0 V,
CL = 15 pF
MR & MS
CP
MS
CP
QO, Q
*The number of Clock Pulses required between the t
1.3 V
t
PHL
Q
1.3 V
t
PLH
3
t
W
Figure 2
t
W
Figure 3
and t
PHL
1.3 V
t
rec
1.3 V
1.3 V
1.3 V
t
rec
1.3 V
1.3 V
measurements can be determined from the Truth Table.
PLH
FAST AND LS TTL DATA
5-3
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