Page 1
SN54/74LS398
QUAD 2-PORT REGISTER
The SN54/74LS398 and SN54/74LS399 are Quad 2-Port Registers. They
are the logical equivalent of a quad 2-input multiplexer followed by a quad 4-bit
edge-triggered register. A Common Select input selects between two 4-bit input ports (data sources). The selected data is transferred to the output register
on the LOW-to-HIGH transition of the Clock input. The SN54/74LS398 features both Q and Q
• Select From Two Data Sources
• Fully Positive Edge-Triggered Operation
• Both True and Complemented Outputs on SN54/74LS398
• Input Clamp Diodes Limit High-Speed Termination Effects
inputs, while the SN54/74LS399 has only Q outputs.
CONNECTION DIAGRAM DIP (TOP VIEW)
V
CC
20 19
QdQ
dIodI1d
18 17 16 15 14 13
I
1c
I
0c
Q
c
QcCP
12 11
SN54/74LS398
123456
QaQ
S
V
CC
16 15
aI0aI1aI1bI0bQb
VCC = PIN 20
GND = PIN 10
QdI
0dI1dI1c
14 13 12 11 10 9
7
I
0c
8
Q
c
910
Q
GND
b
CP
SN54/74LS399
QUAD 2-PORT REGISTER
LOW POWER SCHOTTKY
J SUFFIX
CERAMIC
16
1
16
1
16
1
CASE 620-09
N SUFFIX
PLASTIC
CASE 648-08
D SUFFIX
SOIC
CASE 751B-03
SN54/74LS399
123456
S
QaI
0aI1aI1bI0bQb
VCC = PIN 16
GND = PIN 8
PIN NAMES LOADING (Note a)
S Common Select Input 0.5 U.L. 0.25 U.L.
CP Clock (Active HIGH Going Edge) Input 0.5 U.L. 0.25 U.L.
I0a–I0dData Inputs From Source 0 0.5 U.L. 0.25 U.L.
I1a–I0dData Inputs From Source 1 0.5 U.L. 0.25 U.L.
Qa–QdRegister True Outputs (Note b) 10 U.L. 5 (2.5) U.L.
Qa–QdRegister Complementary Outputs
NOTES:
a) 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.
b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial
(74) T emperature Ranges.
(Note b)
8
7
GND
HIGH
10 U.L. 5 (2.5) U.L.
LOW
FAST AND LS TTL DAT A
5-1
20
1
20
1
20
1
ORDERING INFORMATION
SN54LSXXXJ Ceramic
SN74LSXXXN Plastic
SN74LSXXXDW SOIC
SN74LSXXXD SOIC
J SUFFIX
CERAMIC
CASE 732-03
N SUFFIX
PLASTIC
CASE 738-03
DW SUFFIX
SOIC
CASE 751D-03
Page 2
FUNCTIONAL BLOCK DIAGRAM
SN54/74LS398 • SN54/74LS399
I
OA
S
I
IA
I
OB
I
IB
I
OC
I
IC
I
OD
I
ID
S
R
S
R
S
R
S
R
Q
A
*
Q
A
Q
B
*
Q
B
Q
C
*
Q
C
Q
D
*
Q
D
* SN54/74LS398 only
FUNCTIONAL DESCRIPTION
The SN54 /74LS398 and SN54/74LS399 are high-speed
Quad 2-Port Registers. They select four bits of data from two
sources (Ports) under the control of a common Select Input
(S). The selected data is transferred to a 4-Bit Output Register
synchronous with the LOW-to-HIGH transition of the Clock in-
FUNCTION TABLE
INPUTS OUTPUTS
S I
I I X L H
I h X H L
h X I L H
h X h H L
*SN54/74LS398 only
I = LOW Voltage Level one setup time pior to the LOW-to-HIGH clock transition
h = HIGH Voltage Level one setup time prior to the LOW-to-HIGH clock transition
L = LOW Voltage Level
H = HIGH Voltage Level
X = Immaterial
0
put (CP). The 4-Bit RS type output register is fully edge-triggered. The Data inputs (I) and Select inputs (S) must be stable
only a setup time prior to and hold time after the LOW-to-HIGH
transition of the Clock input for predictable operation. The
SN54/74LS398 has both Q and Q
I
1
Q Q*
Outputs available.
FAST AND LS TTL DATA
5-2
Page 3
SN54/74LS398 • SN54/74LS399
VILI
LOW Volt
V
pg
VOHOutput HIGH Volt
CC
,
OH
,
IN IH
VOLOutput LOW Volt
V
V
V
IIHI
HIGH C
t
GUARANTEED OPERATING RANGES
Symbol Parameter Min Typ Max Unit
V
CC
T
A
I
OH
I
OL
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Symbol Parameter
V
IH
V
IK
I
IL
I
OS
I
CC
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
Supply Voltage 54
Operating Ambient Temperature Range 54
Output Current — High 54, 74 –0.4 mA
Output Current — Low 54
Limits
Min Typ Max
Input HIGH Voltage 2.0 V
nput
Input Clamp Diode Voltage –0.65 –1.5 V VCC = MIN, IIN = –18 mA
nput
Input LOW Current –0.4 mA VCC = MAX, VIN = 0.4 V
Short Circuit Current (Note 1) –20 –100 mA VCC = MAX
Power Supply Current 13 mA VCC = MAX
age
age
age
urren
54
74
54 2.5 3.5 V
74 2.7 3.5 V
54, 74 0.25 0.4 V IOL = 4.0 mA
74 0.35 0.5 V IOL = 8.0 mA
74
74
74
0.7
0.8
20 µA VCC = MAX, VIN = 2.7 V
0.1 mA VCC = MAX, VIN = 7.0 V
4.5
4.75
–55
0
Unit Test Conditions
Guaranteed Input HIGH Voltage for
All Inputs
Guaranteed Input LOW Voltage for
All Inputs
VCC = MIN, IOH = MAX, VIN = V
or VIL per Truth Table
5.0
5.0
25
25
5.5
5.25
125
70
4.0
8.0
VCC = VCC MIN,
=
IN
IL
per Truth Table
or
IH
IH
V
°C
mA
AC CHARACTERISTICS (T
= 25°C, VCC = 5.0 V)
A
Symbol Parameter
t
PLH
t
PHL
Propagation Delay,
Clock to Output Q
Limits
Min Typ Max
18
21
27
32
FAST AND LS TTL DATA
5-3
Unit Test Conditions
ns
VCC = 5.0 V
CL = 15 pF
Page 4
SN54/74LS398 • SN54/74LS399
V
5.0 V
AC SETUP REQUIREMENTS (T
Symbol Parameter
t
W
t
s
t
s
t
h
Clock Pulse Width 20 ns
Data Setup Time 25 ns
Select Setup Time 45 ns
Hold Time, Any Input 0 ns
= 25°C)
A
Min Typ Max
DEFINITIONS OF TERMS
SETUP TIME(ts) — is defined as the minimum time required
for the correct logic level to be present at the logic input prior to
the clock transition from LOW-to-HIGH in order to be recognized and transferred to the outputs.
HOLD TIME(th) — is defined as the minimum time following
AC WAVEFORMS
I0I
*
1
t
CP
Q
1.3 V 1.3 V
t
t
W(L)
h(L)
t
PHL
1.3 V
s(L)
1.3 V
ts(H)
t
W(H)
t
PLH
1.3 V
t
h(H)
1.3 V
Limits
Unit Test Conditions
=
CC
the clock transition from LOW-to-HIGH that the logic level
must be maintained at the input in order to ensure continued
recognition. A negative Hold Time indicates that the correct
logic level may be released prior to the clock transition from
LOW-to-HIGH and still be recognized.
S*
1.3 V 1.3 V
t
t
s(L)
CP
Q or Q
1.3 V
h(L)
1.3 V
= 0 t
ts(H)
Q = I
0
1.3 V
h(H)
1.3 V
= 0
Q = I
1
Figure 1 Figure 2
1.3 V
1.3 V
t
PLH
1.3 V
t
PHL
CP
Q
Q
1.3 V
1.3 V
t
PHL
1.3 V
t
PLH
Figure 3
*The shaded areas indicate when the input is permitted to change for predictable output performance.
FAST AND LS TTL DATA
5-4
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