Page 1
DUAL 4-INPUT MULTIPLEXER
WITH 3-STATE OUTPUTS
The LSTTL/MSI SN54/74LS353 is a Dual 4-Input Multiplexer with 3-state
outputs. It can select two bits of data from four sources using common select
inputs. The outputs may be individually switched to a high impedance state
with a HIGH on the respective Output Enable (E0) inputs, allowing the outputs
to interface directly with bus oriented systems. It is fabricated with the Schottky barrier diode process for high speed and is completely compatible with all
TTL families.
• Inverted Version of the SN54/74LS253
• Schottky Process for High Speed
• Multifunction Capability
• Input Clamp Diodes Limit High Speed Termination Effects
CONNECTION DIAGRAM DIP (TOP VIEW)
V
E0bS0I3bI
CC
16 15
2b
14 13 12 11 10 9
I
I
1b
0b
Z
b
NOTE:
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual In-Line Package.
SN54/74LS353
DUAL 4-INPUT MULTIPLEXER
WITH 3-STATE OUTPUTS
LOW POWER SCHOTTKY
J SUFFIX
CERAMIC
16
1
16
1
CASE 620-09
N SUFFIX
PLASTIC
CASE 648-08
123456
E
S1I
0a
PIN NAMES LOADING (Note a)
S0, S
1
Multiplexer A
E
0a
I0A–I
3a
Z
a
Multiplexer B
E
0b
I0b–I
3b
Z
b
NOTES:
a) 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.
b) The Output LOW drive factor is 7.5 U.L. for Military (54) and 15 U.L. for Commercial
(74) T emperature Ranges. The Output HIGH drive factor is 25 U.L. for Military and 65 U.L.
for Commercial T emperature Ranges.
3aI2aI1aI0aZa
Common Select Inputs 0.5 U.L. 0.25 U.L.
Output Enable (Active LOW) Input 0.5 U.L. 0.25 U.L.
Multiplexer Inputs 0.5 U.L. 0.25 U.L.
Multiplexer Output (Note b) 65 (25) U.L. 15 (7.5) U.L.
Output Enable (Active LOW) Input 0.5 U.L. 0.25 U.L.
Multiplexer Inputs 0.5 U.L. 0.25 U.L.
Multiplexer Output (Note b) 65 (25) U.L. 15 (7.5) U.L.
7
GND
8
HIGH
LOW
16
1
ORDERING INFORMATION
SN54LSXXXJ Ceramic
SN74LSXXXN Plastic
SN74LSXXXD SOIC
LOGIC SYMBOL
16543 10111213
E
I0aI1aI2aI
14
0a
S
0
2
S
1
Z
a
79
CASE 751B-03
I0bI1bI2bI
3a
D SUFFIX
SOIC
Z
b
3b
15
E
0b
FAST AND LS TTL DAT A
5-1
VCC = PIN 16
GND = PIN 8
Page 2
SN54/74LS353
DATA INPUTS
OUTPUT
LOGIC DIAGRAM
I
E
3bI2bI1bI0b
0b
1112 101315
VCC = PIN 16
9
Z
b
GND = PIN 8
FUNCTIONAL DESCRIPTION
The SN54 / 74LS353 contains two identical 4-input Multi-
plexers with 3-state outputs. They select two bits from four
sources selected by common select inputs (S0, S1). The
4-input multiplexers have individual Output Enable (E0a, E0b)
Z
= E0a • (I0a • S1 • S0 + I1a • S1 • S0 + I2a • S1 • S0 + I3a • S1 • S0)
a
= E0b • (I0b • S1 • S0 + I1b • S1 • S0 + I2b • S1 • S0 + I3b • S1 • S0)
Z
b
S
S
0
14 126
= PIN NUMBERS
I
1
3aI2aI1aI0a
345
E
0a
7
Z
a
inputs which when HIGH, forces the outputs to a high
impedance (high Z) state.
The logic equations for the outputs are shown below:
If the outputs of 3-state devices are tied together, all but one
device must be in the high impedance state to avoid high
currents that would exceed the maximum ratings. Designers
TRUTH TABLE
SELECT
INPUTS
S
0
X X X X X X H (Z)
L LLXX X L H
LLHXXX L L
HLXLX X L H
HLXHX X L L
LHXXL X L H
LHXXH X L L
HHXXX L L H
HHXXXH L L
H = HIGH Level
L = LOW Level
X = Immaterial
(Z) = High Impedance (off)
Address inputs S0 and S1 are common to both sections.
S
1
I
0
I
1
should ensure that Output Enable signals to 3-state devices
whose outputs are tied together are designed so that there is
no overlap.
OUTPUT
ENABLE
I
2
I
3
E
0
Z
FAST AND LS TTL DATA
5-2
Page 3
SN54/74LS353
VILI
LOW Volt
V
pg
VOHOutput HIGH Volt
CC
,
OH
,
IN IH
V
pg
V
V
V
IIHI
HIGH C
t
CC
CC
C
F
C
F
GUARANTEED OPERATING RANGES
Symbol Parameter Min Typ Max Unit
V
CC
T
A
I
OH
I
OL
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Symbol Parameter
V
IH
V
IK
OL
I
OZH
I
OZL
I
IL
I
OS
I
CC
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS (T
Symbol Parameter
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PLZ
t
PHZ
Supply Voltage 54
Operating Ambient Temperature Range 54
Output Current — High 54
Output Current — Low 54
Limits
Min Typ Max
Input HIGH Voltage 2.0 V
nput
Input Clamp Diode Voltage –0.65 –1.5 V VCC = MIN, IIN = –18 mA
Output LOW Voltage
QA–Q
Output Off Current HIGH 20 µA VCC = MAX, V
Output Off Current LOW –20 µA VCC = MAX, V
nput
Input LOW Current –0.4 mA VCC = MAX, VIN = 0.4 V
Short Circuit Current (Note 1) –20 –130 mA VCC = MAX
Power Supply Current
Total, Output 3-State
Total, Output LOW 12
Propagation Delay,
Data to Output
Propagation Delay,
Select to Output
Output Enable Time
to HIGH Level
Output Enable Time
to LOW Level
Output Disable Time
to LOW Level
Output Disable Time
to HIGH Level
age
age
H
urren
= 25°C, VCC = 5.0 V)
A
54
74
54 2.4 3.4 V
74 2.4 3.1 V
54, 74 0.25 0.4 V IOL = 12 mA
74 0.35 0.5 V IOL = 24 mA
Limits
Min Typ Max
11
13
20
21
11 23 ns Figures 4, 5
15 23 ns Figures 3, 5
12 27 ns Figures 3, 5
27 41 ns Figures 4, 5
74
74
74
74
0.7
0.8
20 µA VCC = MAX, VIN = 2.7 V
0.1 mA VCC = MAX, VIN = 7.0 V
14
25
20
45
32
4.5
4.75
–55
0
Unit Test Conditions
Guaranteed Input HIGH Voltage for
All Inputs
Guaranteed Input LOW Voltage for
All Inputs
VCC = MIN, IOH = MAX, VIN = V
or VIL per Truth Table
mA VCC = MAX
Unit Test Conditions
ns Figure 1
ns Figure 1 or 2
5.0
5.0
25
25
OUT
OUT
5.5
5.25
125
70
–1.0
–2.6
12
24
IH
VCC = VCC MIN,
=
or
IN
IL
= 15 p
L
= 5.0 p
L
IH
per Truth Table
= 2.7 V
= 0.4 V
V
°C
mA
mA
FAST AND LS TTL DATA
5-3
Page 4
SN54/74LS353
3-STATE WAVEFORMS
V
IN
V
OUT
V
E
V
E
V
TO OUTPUT
UNDER TEST
1.3 V 1.3 V
t
PLH
1.3 V
Figure 1
1.5 V 1.5 V
t
PZL
OUT
1.5 V
Figure 3
V
CC
R
SW1
1.3 V
t
PHL
1.3 V
t
PHL
1.3 V
V
V
IN
OUT
1.3 V
t
PLH
1.3 V
Figure 2
V
0.5 V
t
PLZ
≈
V
1.5 V
OL
E
V
E
t
PZH
V
OUT
1.5 V 1.5 V
t
PHZ
1.5 V
≥
V
0.5 V
≈
OH
1.5 V
Figure 4
AC LOAD CIRCUIT
SWITCH POSITIONS
L
SYMBOL SW1 SW2
t
PZH
t
PZL
t
PLZ
t
PHZ
Open Closed
Closed Open
Closed Closed
Closed Closed
Ω
5.0 k
SW2CL*
* Includes Jig and Probe Capacitance.
Figure 5
FAST AND LS TTL DATA
5-4
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