Datasheet SN54LS322AJ, SN74LS322AN, SN74LS322ADW Datasheet (Motorola)

5-1

FAST AND LS TTL DATA

8-BIT SHIFT REGISTERS
WITH SIGN EXTEND

These 8-bit shift registers have multiplexed input/output data ports to
accomplish full 8-bit data handling in a single 20-pin package. Serial data may
enter the shift-right register through either D0 or D1 inputs as selected by the
data select pin. A serial output is also provided. Synchronous parallel loading
is achieved by taking the register enable and the S/P

inputs low. This places
the three-state input/output ports in the data input mode. Data is entered on
the low-to-high clock transition. The data extend function repeats the sign in
the QA flip-flop during shifting. An overriding clear input clears the internal
registers when taken low whether the outputs are enabled or off. The output
enable does not affect synchronous operation of the register.

• Multiplexed Inputs/Outputs Provide Improved Bit Density

• Sign Extend Function

• Direct Overriding Clear

• 3-State Outputs Drive Bus Lines Directly

V

CC

DATA

SELECT

SIGN

EXTEND

D1 B/QBD/QDF/QFH/QHQ/HCLOCK

D0 A/QAC/QCE/QEG/Q

G

S/P

REGISTER

ENABLE

OUTPUT
ENABLE

CLEAR GND

(TOP VIEW)

18 17 16 15 14 13

1 2 3 4 5 6 7

20

19

8 9 10

12 11

DS SE D1 B/QBD/QDF/QFH/GHQ/

H

G

CK

S/P D0 A/QAC/QCE/QEG/QGOE CLR

GUARANTEED OPERATING RANGES

Symbol Parameter Min Typ Max Unit

V

CC

Supply Voltage 54

74

4.5

4.75

5.0

5.0

5.5

5.25

V

T

A

Operating Ambient Temperature Range 54

74

–55

0

25
25

125

70

°C

I

OH

Output Current — High QH′ 54, 74 –0.4 mA

I

OL

Output Current — Low QH′

QH′

54
74

4.0

8.0

mA

I

OH

Output Current — High QA–Q

H

QA–Q

H

54
74

–1.0
–2.6

mA

I

OL

Output Current — Low QA–Q

H

QA–Q

H

54
74

12
24

mA

SN54/74LS322A

8-BIT SHIFT REGISTERS

WITH SIGN EXTEND

LOW POWER SCHOTTKY

ORDERING INFORMATION

SN54LSXXXJ Ceramic
SN74LSXXXN Plastic
SN74LSXXXDW SOIC

20

1

J SUFFIX

CERAMIC

CASE 732-03

20

1

N SUFFIX

PLASTIC

CASE 738-03

20

1

DW SUFFIX

SOIC

CASE 751D-03

5-2

FAST AND LS TTL DATA

SN54/74LS322A

BLOCK DIAGRAM

REGISTER

ENABLE

G

S/P

SIGN

EXTEND

SE

D1

DATA

SELECT

DS

D0

CLOCK

CLEAR

OUTPUT
ENABLE

OE

(8)

(9)

(11)

(3)

(19)

(18)

(2)

(1)

(12)

(13)

(7)(16)

(4)

(17)

CK

D

Q

Q

CLR

CK

D

Q

Q

CLR

CK

D

Q

Q

CLR

CK

D

Q

Q

CLR

A/Q

A

B/Q

B

G/Q

G

H/Q

H

FOUR
IDENTICAL
CHANNELS

NOT

SHOWN

Q

H

FUNCTION TABLE

INPUTS INPUTS/OUTPUTS

OPERATION

CLEAR

REGISTER

ENABLE

S/P

SIGN

EXTEND

DATA

SELECT

OUTPUT
ENABLE

CLOCK A/QAB/QBC/QC H/Q

H

OUTPUT

QH′

Clear L H X X X L X L L L L L

L X H X X L X L L L L L

Hold H H X X X L X Q

A0QB0QC0QH0

Q

H0

H L H H L L ↑ D0Q

AnQBnQGn

Q

Gn

Shift Right

H L H H H L ↑ D1Q

AnQBnQGn

Q

Gn

Sign Extend H L H L X L ↑ Q

AnQAnQBnQGn

Q

Gn

Load H L L X X X ↑ a b c h h

When the output enable is high, the eight input/output terminals are disabled to the high-impedance state; however, sequential operation or
clearing of the register is not affected. If both the register enable input and the S/P

input are low while the clear input is low, the register is

cleared while the eight input/output terminals are disabled to the high-impedance state.

H = HIGH Level (steady state)
L = LOW Level (steady state)
X = Irrelevant (any input, including transitions)
↑ = Transition from LOW to HIGH level
Q

A0…QH0

= the level of QA through QH, respectively, before the indicated steady-state conditions were established

Q

An…QHn

= the level of QA through QH, respectively, before the most recent ↑ transition of the clock
D0, D1 = the level of steady-state inputs at inputs D0 and D1 respectively
a…h = the level of steady-state inputs at inputs A through H respectively

…

5-3

FAST AND LS TTL DATA

SN54/74LS322A

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)

Limits

Symbol

Parameter

Min Typ Max

Unit

Test Conditions

V

IH

Input HIGH Voltage 2.0 V

Guaranteed Input HIGH Voltage for
All Inputs

54 0.7

Guaranteed Input LOW Voltage for

VILInput LOW Voltage

74 0.8

V

Guaranteed Input LOW Voltage for
All Inputs

V

IK

Input Clamp Diode Voltage –0.65 –1.5 V VCC = MIN, IIN = –18 mA
Output HIGH Voltage

54 2.4 3.2 V

V

OH

Output HIGH Voltage
QA–Q

H

74 2.4 3.2 V

VCC = MIN, IOH = MAX

Output HIGH Voltage

54 2.5 3.4 V

V

OH

Output HIGH Voltage
QH′

74 2.7 3.4 V

VCC = MIN, IOH = MAX

Output LOW Voltage

54, 74 0.25 0.4 V IOL = 12 mA

VCC = VCC MIN,

V

OL

Output LOW Voltage
QA–Q

H

74 0.35 0.5 V IOL = 24 mA

VIN = VIL or V

IH

per Truth Table

Output LOW Voltage

54, 74 0.4 V IOL = 4.0 mA

VCC = VCC MIN,

V

OL

Output LOW Voltage
QH′

74 0.5 V IOL = 8.0 mA

VIN = VIL or V

IH

per Truth Table

I

OZH

Output Off Current HIGH
QA–Q

H

40 µA VCC = MAX, V

OUT

= 2.7 V

I

OZL

Output Off Current LOW
QA–Q

H

–400 µA VCC = MAX, V

OUT

= 0.4 V

Other 20 µA
A–H,

Data Select

40 µA

VCC = MAX, VIN = 2.7 V

Sign Extend 60 µA

IIHInput HIGH Current

Other 0.1 mA
Data Select 0.2 mA

VCC = MAX, VIN = 7.0 V

Sign Extend 0.3 mA

CC

= MAX, VIN = 7.0 V

A–H 0.1 mA VCC = MAX, VIN = 5.5 V
Other –0.4 mA

I

IL

Input LOW Current

Data Select –0.8 mA

VCC = MAX, VIN = 0.4 V

IL

Sign Extend –1.2 mA

CC

= MAX, VIN = 0.4 V

Short Circuit Current

QH′ –20 –100 mA VCC = MAX

I

OS

Short Circuit Current

(Note 1)

QA–Q

H

–30 –130 mA VCC = MAX

I

CC

Power Supply Current 60 mA VCC = MAX

Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.

5-4

FAST AND LS TTL DATA

SN54/74LS322A

AC CHARACTERISTICS (T

A

= 25°C, VCC = 5.0 V)

Limits

Symbol

Parameter

Min Typ Max

Unit

Test Conditions

f

MAX

Maximum Clock Frequency 25 35 MHz

t

PHL

t

PLH

Propagation Delay, Clock
to QH′

26
22

35
33

ns

CL = 15 pF

t

PHL

Propagation Delay, Clear
to QH′

27 35 ns

L

= 15 pF

t

PHL

t

PLH

Propagation Delay, Clock
to QA–Q

H

22
16

33
25

ns

t

PHL

Propagation Delay, Clear
to QA–Q

H

22 35 ns

CL = 45 pF,
RL = 667 Ω

t

PZH

t

PZL

Output Enable Time

15
15

35
35

ns

t

PHZ

t

PLZ

Output Disable Time

15
15

25
25

ns CL = 5.0 pF

AC SETUP REQUIREMENTS (T

A

= 25°C, VCC = 5.0 V)

Limits

Symbol

Parameter

Min Typ Max

Unit

Test Conditions

t

W

Clock Pulse Width HIGH 25 ns

t

W

Clock Pulse Width LOW 15 ns

t

W

Clear Pulse Width LOW 20 ns

t

s

Data Setup Time 20 ns

t

s

Select Setup Time 15 ns

VCC = 5.0 V

t

h

Data Hold Time 0 ns

t

h

Select Hold Time 10 ns

t

rec

Recovery Time 20 ns

DEFINITIONS OF TERMS

SETUP TIME (ts) — is defined as the minimum time required
for the correct logic level to be present at the logic input prior to
the clock transition from LOW-to-HIGH in order to be recog­nized and transferred to the outputs.

HOLD TIME (th) — is defined as the minimum time following
the clock transition from LOW-to-HIGH that the logic level
must be maintained at the input in order to ensure continued

recognition. A negative HOLD TIME indicates that the correct
logic level may be released prior to the clock transition from
LOW-to-HIGH and still be recognized.

RECOVERY TIME (t

rec

) — is defined as the minimum time
required between the end of the reset pulse and the clock
transition from LOW-to-HIGH in order to recognize and
transfer HIGH Data to the Q outputs.