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Semiconductor Components Industries, LLC, 1999
December, 1999 – Rev. 6
1 Publication Order Number:
SN74LS299/D
SN74LS299
8-Bit Shift/Storage Register
with 3-State Outputs
The SN74LS299 is an 8-Bit Universal Shift/Storage Register with
3-state outputs. Four modes of operation are possible: hold (store),
shift left, shift right and load data.
The parallel load inputs and flip-flop outputs are multiplexed to
reduce the total number of package pins. Separate outputs are provided
for flip-flops Q
0
and Q7 to allow easy cascading. A separate active
LOW Master Reset is used to reset the register.
• Common I/O for Reduced Pin Count
• Four Operation Modes: Shift Left, Shift Right, Load and Store
• Separate Shift Right Serial Input and Shift Left Serial Input for Easy
Cascading
• 3-State Outputs for Bus Oriented Applications
• Input Clamp Diodes Limit High-Speed Termination Effects
• ESD > 3500 Volts
GUARANTEED OPERATING RANGES
Symbol Parameter Min Typ Max Unit
V
CC
Supply Voltage 4.75 5.0 5.25 V
T
A
Operating Ambient
T emperature Range
0 25 70 °C
I
OH
Output Current – High
Q
0
, Q
7
–0.4 mA
I
OL
Output Current – Low
Q
0
, Q
7
8.0 mA
I
OH
Output Current – High
I/O
0
– 1/O
7
–2.6 mA
I
OL
Output Current – Low
I/O
0
– 1/O
7
24 mA
LOW
POWER
SCHOTTKY
Device Package Shipping
ORDERING INFORMATION
SN74LS299N 16 Pin DIP 1440 Units/Box
SN74LS299DW 16 Pin
SOIC
DW SUFFIX
CASE 751D
http://onsemi.com
2500/Tape & Reel
PLASTIC
N SUFFIX
CASE 738
20
1
20
1
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2
CONNECTION DIAGRAM DIP (TOP VIEW)
Clock Pulse (Active Positive–Going Edge) Input
Serial Data Input for Right Shift
Serial Data Input for Left Shift
Parallel Data Input or
Parallel Output (3–State)
3–State Output Enable (Active LOW) Inputs
Serial Outputs
Asynchronous Master Reset (Active LOW) Input
Mode Select Inputs
CP
DS0
DS7
I/O
n
OE1, OE
2
Q0, Q
7
MR
S0, S
1
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
65 U.L.
0.5 U.L.
10 U.L.
0.5 U.L.
1 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
15 U.L.
0.25 U.L.
5 U.L.
0.25 U.L.
0.5 U.L.
NOTES:
a) 1 TTL Unit Load (U.L.) = 40 mA HIGH/1.6 mA LOW.
HIGH LOW
(Note a)LOADING
PIN NAMES
18 17 16 15 14 13
123456
7
20 19
8
V
CC
S
0
S1Ds7Q7I/O
7
I/O
3
I/O
5
I/O
1
OE1OE2I/O6I/O4I/O2I/O0Q
0
910
MR
GND
12 11
CP DS
0
NOTE:
The Flatpak version has the same
pinouts (Connection Diagram) as
the Dual In-Line Package.
S1S
0
DS
0
CLOCK
Q
0
MR
OE
1
OE
2
D
CLR
Q
CK
I/O
0
I/O
1
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
D
S7
Q
7
VCC = PIN 20
GND = PIN 10
= PIN NUMBERS
14
1
2
67
3
8
45
9
11
12
13 15 16
17
18
19
D
CLR
Q
CK
D
CLR
Q
CK
D
CLR
Q
CK
D
CLR
Q
CK
D
CLR
Q
CK
D
CLR
Q
CK
D
CLR
Q
CK
LOGIC DIAGRAM
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FUNCTION TABLE
INPUTS RESPONSE
MR S1S0OE1OE2CP DS0DS
7
L X X H X X X X
;
L X X X H X X X
Asynchronous Reset Q
0
= Q
7
= LOW
L H H X X X X X
I/O Voltage Undetermined
L L X L L X X X Asynchronous Reset; Q
0
= Q7 = LOW
L X L L L X X X I/O V oltage LOW
H L H X X D X Shift Right; D³Q0; Q0³
Q1; etc.
H L H L L D X Shift Right; D³Q0 & I/O0; Q0³
O1 & I/O1; etc.
H H L X X X D Shift Left; D³Q7; Q7³
Q6; etc.
H H L L L X D Shift Left; D³Q
7
& I/O7; Q7³
Q6 & I/O6; etc.
H H H X X X X Parallel Load; I/On³
Q
n
H L L H X X X X
H L L X H X X X
Hold: I/O Voltage undetermined
H L L L L X X X Hold: I/On = Q
n
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
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DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits
Symbol Parameter
Min Typ Max
Unit Test Conditions
V
IH
Input HIGH Voltage 2.0 V
Guaranteed Input HIGH Voltage for
All Inputs
V
IL
Input LOW Voltage
0.8
V
Guaranteed Input LOW Voltage for
All Inputs
V
IK
Input Clamp Diode Voltage –0.65 –1.5 V VCC = MIN, IIN = –18 mA
V
OH
Output HIGH Voltage
I/O
0
–I/O
7
2.4 3.1 V
VCC = MIN, IOH = MAX
V
OH
Output HIGH Voltage
Q
0
, Q
7
2.7 3.4 V
VCC = MIN, IOH = MAX
Output LOW Voltage
0.25 0.4 V IOL = 12 mA
VCC = VCC MIN,
V
OL
g
I/O0–I/O
7
0.35 0.5 V IOL = 24 mA
V
IN
=
V
IL
or
V
IH
per Truth Table
Output LOW Voltage
0.4 V IOL = 4.0 mA
VCC = VCC MIN,
V
OL
g
I/O0–I/O
7
0.5 V IOL = 8.0 mA
V
IN
=
V
IL
or
V
IH
per Truth Table
I
OZH
Output Off Current HIGH
I/O
0
–I/O
7
40 µA VCC = MAX, V
OUT
= 2.7 V
I
OZL
Output Off Current LOW
I/O
0
–I/O
7
–400 µA VCC = MAX, V
OUT
= 0.4 V
Others 20 µA
S0, S1,
I/O
0
–I/O
7
40 µA
VCC = MAX, VIN = 2.7 V
I
IH
Input HIGH Current
Others 0.1 mA
S0, S
1
0.2 mA
V
CC
=
MAX, V
IN
= 7.0
V
I/O0–I/O
7
0.1 mA VCC = MAX, VIN = 5.5 V
p
Others –0.4 mA
IILInput LOW Current
S0, S
1
–0.8 mA
V
CC
=
MAX, V
IN
= 0.4
V
I
OS
Short Circuit Current
Q0, Q
7
–20 –100 mA VCC = MAX
(Note 1)
I/O0–I/O
7
–30 –130 mA VCC = MAX
I
CC
Power Supply Current 53 mA VCC = MAX
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
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AC CHARACTERISTICS (T
A
= 25°C, VCC = 5.0 V)
Limits
Symbol Parameter
Min Typ Max
Unit Test Conditions
f
MAX
Maximum Clock Frequency 25 35 MHz
t
PHL
t
PLH
Propagation Delay, Clock
to Q
0
or Q
7
26
22
39
33
ns
CL = 15 pF
t
PHL
Propagation Delay, Clear
to Q
0
or Q
7
27 40 ns
t
PHL
t
PLH
Propagation Delay, Clock
to I/O
0
–I/O
7
26
17
39
25
ns
t
PHL
Propagation Delay, Clear
to I/O
0
–I/O
7
26 40 ns
CL = 45 pF,
R
L
= 667 Ω
t
PZH
t
PZL
Output Enable Time
13
19
21
30
ns
t
PHZ
t
PLZ
Output Disable Time
10
10
15
15
ns CL = 5.0 pF
AC SETUP REQUIREMENTS (T
A
= 25°C, VCC = 5.0 V)
Limits
Symbol Parameter
Min Typ Max
Unit Test Conditions
t
W
Clock Pulse Width HIGH 25 ns
t
W
Clock Pulse Width LOW 13 ns
t
W
Clear Pulse Width LOW 20 ns
t
s
Data Setup Time 20 ns
t
s
Select Setup Time 35 ns
V
CC
= 5.0
V
t
h
Data Hold Time 0 ns
t
h
Select Hold Time 10 ns
t
rec
Recovery Time 20 ns
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1.3 V
1.3 V 1.3 V
1.3 V
V
IN
V
OUT
t
PLH
t
PHL
1.3 V
1.3 V
V
IN
V
OUT
1.3 V
t
PLH
t
PHL
1.3 V
Figure 1. Figure 2.
Figure 3. Figure 4.
1.5 V 1.5 V
1.5 V ≈ 1.5 V
1.5 V 1.5 V
1.5 V ≈ 1.5 V
V
E
V
E
V
OUT
t
PZL
t
PLZ
V
OL
0.5 V
V
E
V
E
V
OUT
t
PZH
t
PHZ
0.5 V
≥ V
OH
3-STATE WAVEFORMS
AC LOAD CIRCUIT
SW2CL*
5 kΩ
SW1
V
CC
R
L
TO OUTPUT
UNDER TEST
* Includes Jig and Probe Capacitance.
SWITCH POSITIONS
Closed
Open
Closed
Closed
Open
Closed
Closed
Closed
t
PZH
t
PZL
t
PLZ
t
PHZ
SW2SW1SYMBOL
Figure 5.
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P ACKAGE DIMENSIONS
N SUFFIX
PLASTIC PACKAGE
CASE 738–03
ISSUE E
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
M
L
J
20 PL
M
B
M
0.25 (0.010) T
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A 25.66 27.171.010 1.070
B 6.10 6.600.240 0.260
C 3.81 4.570.150 0.180
D 0.39 0.550.015 0.022
G 2.54 BSC0.100 BSC
J 0.21 0.380.008 0.015
K 2.80 3.550.110 0.140
L 7.62 BSC0.300 BSC
M 0 15 0 15
N 0.51 1.010.020 0.040
____
E
1.27 1.770.050 0.070
1
11
10
20
–A–
SEATING
PLANE
K
N
FG
D
20 PL
–T–
M
A
M
0.25 (0.010) T
E
B
C
F
1.27 BSC0.050 BSC
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751D–05
ISSUE F
20
1
11
10
B20X
H10X
C
L
18X
A1
A
SEATING
PLANE
q
h X 45
_
E
D
M
0.25
M
B
M
0.25
SAS
B
T
e
T
B
A
DIM MIN MAX
MILLIMETERS
A 2.35 2.65
A1 0.10 0.25
B 0.35 0.49
C 0.23 0.32
D 12.65 12.95
E 7.40 7.60
e 1.27 BSC
H 10.05 10.55
h 0.25 0.75
L 0.50 0.90
q
0 7
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION SHALL
BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT
MAXIMUM MATERIAL CONDITION.
__
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