Datasheet SN74ls299 Datasheet

8-BIT SHIFT/STORAGE REGISTER WITH 3-STATE OUTPUTS

SN54/74LS299

The SN54/74LS299 is an 8-Bit Universal Shift/Storage Register with 3-state outputs. Four modes of operation are possible: hold (store), shift left, shift right and load data.

The parallel load inputs and flip-flop outputs are multiplexed to reduce the total number of package pins. Separate outputs are provided for flip-flops Q and Q7 to allow easy cascading. A separate active LOW Master Reset is used to reset the register.

• Common I/O for Reduced Pin Count

• Four Operation Modes: Shift Left, Shift Right, Load and Store

• Separate Shift Right Serial Input and Shift Left Serial Input for Easy

Cascading

• 3-State Outputs for Bus Oriented Applications

• Input Clamp Diodes Limit High-Speed Termination Effects

• ESD > 3500 Volts

CONNECTION DIAGRAM DIP (TOP VIEW)

V

S1Ds7Q7I/O

CC

20 19

1234 56

S

0

18 17 16 15 14 13

OE

I/O6I/O4I/O2I/O0Q

1OE2

I/O

7

5

I/O

3

7

I/O

8

1

0

CP DS

0

12 11

910

MR

GND

NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package.

8-BIT SHIFT/STORAGE REGISTER

WITH 3-STATE OUTPUTS

0

LOW POWER SCHOTTKY

20

1

20

1

20

1

ORDERING INFORMATION

SN54LSXXXJ Ceramic SN74LSXXXN Plastic SN74LSXXXDW SOIC

J SUFFIX

CERAMIC

CASE 732-03

N SUFFIX

PLASTIC

CASE 738-03

DW SUFFIX

SOIC

CASE 751D-03

PIN NAMES LOADING (Note a)

HIGH

CP Clock Pulse (active positive-going edge) Input 0.5 U.L. 0.25 U.L. DS0 Serial Data Input for Right Shift 0.5 U.L. 0.25 U.L. DS7 Serial Data Input for Left Shift 0.5 U.L. 0.25 U.L. I/O

n

OE

, OE

1

Q0, Q MR Asynchronous Master Reset (active LOW) Input 0.5 U.L. 0.25 U.L. S0, S

NOTES: a) 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW. b) The Output LOW drive factor is 2.5 U.L for Military (54) and 5 U.L. for Commercial (74) Temperature Ranges. c) The Output LOW drive factor is 7.5 U.L for Military (54) and 15 U.L. for Commercial (74). The Output HIGH drive factor is 25 U.L. for Military (54) and 65 U.L. for

2

7

1

Commercial (74) T emperature Ranges.

Parallel Data Input or Parallel Output (3-State) (Note c) 3-State Output Enable (active LOW) Inputs 0.5 U.L. 0.25 U.L. Serial Outputs (Note b) 10 U.L. 5 (2.5) U.L.

Mode Select Inputs 1 U.L. 0.5 U.L.

0.5 U.L.

65 (25) U.L.

LOW

0.25 U.L.

15 (7.5) U.L.

FAST AND LS TTL DAT A

5-1

SN54/74LS299

Asynchronous Reset; Q

0

Q

7

LOW

I/O Voltage Undetermined

Hold: I/O Voltage undetermined

DS

0

CLOCK

Q

0

MR

OE

1

OE

2

S1S

19

11

12

8

9 2

3

LOGIC DIAGRAM

0

1

CLR

I/O

D

CK

Q

0

D

CK

CLR

Q

13 15 16

I/O

1

CLR

I/O

D

CK

Q

67

2

CLR

I/O

D

CK

Q

14

3

CLR

I/O

D

CK

Q

4

CLR

I/O

D

CK

Q

5

CLR

I/O

D

CK

Q

45

6

CLR

I/O

D

FUNCTION TABLE

INPUTS RESPONSE

MR S1S0OE1OE2CP DS0DS

L X X H X X X X L X X X H X X X L H H X X X X X

L L X L L X X X Asynchronous Reset; Q0 = Q7 = LOW L X L L L X X X I/O Voltage LOW

H L H X X D X Shift Right; D→Q0; Q0→Q1; etc. H L H L L D X Shift Right; D→Q0 & I/O0; Q0→O1 & I/O1; etc.

H H L X X X D Shift Left; D→Q7; Q7→Q6; etc. H H L L L X D Shift Left; D→Q7 & I/O7; Q7→Q6 & I/O6; etc.

H H H X X X X Parallel Load; I/On→Q H L L H X X X X

H L L X H X X X H L L L L X X X Hold: I/On = Q

H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial

7

=

n

18

D

S7

CK

17

Q

7

VCC = PIN 20 GND = PIN 10

7

= PIN NUMBERS

GUARANTEED OPERATING RANGES

Symbol Parameter Min Typ Max Unit

V

CC

T

A

I

OH

I

OL

I

OH

I

OL

Supply Voltage 54

Operating Ambient Temperature Range 54

Output Current — High Q0, Q Output Current — Low Q0, Q

Output Current — High I/O0–I/O

Output Current — Low I/O0–I/O

7 7

Q0, Q

7

I/O0–I/O

74

4.75 –55

4.5

74

0

54, 74 –0.4 mA

54 74

7 7

54 74

5.0

5.0 25

25

5.5

5.25 125

70

4.0

8.0

–1.0

– 2.6

12 24

V

°C

mA

FAST AND LS TTL DATA

5-2

SN54/74LS299

VILI

LOW Volt

V

pg

V

pg

V

MIN, I

MAX

V

pg

V

MIN, I

MAX

V

pg

V

pg

V

MAX, V

V

IILI

LOW C

t

V

MAX, V

V

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)

Limits

Symbol Parameter

V

IH

V

IK

OH

OL

I

OZH

I

OZL

I

IH

I

OS

I

CC

Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.

Input HIGH Voltage 2.0 V

nput

Input Clamp Diode Voltage –0.65 –1.5 V VCC = MIN, IIN = –18 mA Output HIGH Voltage

I/O0–I/O

Output HIGH Voltage Q0, Q

7

Output LOW Voltage I/O0–I/O

Output Off Current HIGH I/O0–I/O

Output Off Current LOW I/O0–I/O

Input HIGH Current

nput

Short Circuit Current

(Note 1)

Power Supply Current 53 mA VCC = MAX

age

7

Others 20 µA S0, S1,

I/O0–I/O Others 0.1 mA S0, S I/O0–I/O

urren

Others –0.4 mA S0, S Q0, Q I/O0–I/O

54 0.7 74 0.8

54 2.4 3.2 V 74 2.4 3.1 V 54 2.5 3.4 V 74 2.7 3.4 V

54, 74 0.25 0.4 V IOL = 12 mA

74 0.35 0.5 V IOL = 24 mA

54, 74 0.4 V IOL = 4.0 mA

74 0.5 V IOL = 8.0 mA

7

1

7

1

7

Min Typ Max

–400 µA VCC = MAX, V

0.2 mA

0.1 mA VCC = MAX, VIN = 5.5 V

–0.8 mA –20 –100 mA VCC = MAX –30 –130 mA VCC = MAX

Unit Test Conditions

Guaranteed Input HIGH Voltage for All Inputs

Guaranteed Input LOW Voltage for All Inputs

=

CC

=

CC

40 µA VCC = MAX, V

40 µA

VCC = MAX, VIN = 2.7 V

=

CC

=

CC

OH

=

VCC = VCC MIN,

=

IN

per Truth Table VCC = VCC MIN,

=

IN

per Truth Table

= 2.7 V

OUT

= 0.4 V

OUT

= 7.0

IN

= 0.4

IN

or

IL

IH

or

IL

IH

FAST AND LS TTL DATA

5-3

SN54/74LS299

V

AC CHARACTERISTICS (T

Symbol Parameter

f

MAX

t

PHL

t

PLH

t

PHL

t

PHL

t

PLH

t

PHL

t

PZH

t

PZL

t

PHZ

t

PLZ

Maximum Clock Frequency 25 35 MHz Propagation Delay, Clock

to Q0 or Q Propagation Delay, Clear

to Q0 or Q Propagation Delay, Clock

to I/O0–I/O Propagation Delay, Clear

to I/O0–I/O

Output Enable Time

Output Disable Time

= 25°C, VCC = 5.0 V)

A

7

AC SETUP REQUIREMENTS (T

Symbol Parameter

t t t t t t t t

W W W s s h h rec

Clock Pulse Width HIGH 25 ns Clock Pulse Width LOW 13 ns Clear Pulse Width LOW 20 ns Data Setup Time 20 ns Select Setup Time 35 ns Data Hold Time 0 ns Select Hold Time 10 ns Recovery Time 20 ns

= 25°C, VCC = 5.0 V)

A

Limits

Min Typ Max

26 22

27 40 ns

26 17

26 40 ns

13 19

10 10

Limits

Min Typ Max

39 33

39 25

21 30

15 15

Unit Test Conditions

ns

ns CL = 5.0 pF

Unit Test Conditions

CL = 15 pF

CL = 45 pF, RL = 667 Ω

= 5.0

CC

FAST AND LS TTL DATA

5-4

V

1.3 V 1.3 V

IN

t

PLH

V

OUT

1.3 V

Figure 1 Figure 2

SN54/74LS299

3-STATE WAVEFORMS

t

PHL

1.3 V

V

IN

V

OUT

1.3 V t

PLH

1.3 V

1.3 V t

PHL

1.3 V

V

E

V

E

V

TO OUTPUT

UNDER TEST

1.5 V 1.5 V t

PZL

OUT

1.5 V

Figure 3 Figure 4

SW1

V

0.5 V

t

PLZ

≈

V

1.5 V

OL

E

V

E

t

PZH

V

OUT

1.5 V 1.5 V t

PHZ

1.5 V

≥

V

0.5 V

≈

OH

1.5 V

AC LOAD CIRCUIT

V

CC

R

L

SYMBOL SW1 SW2

SWITCH POSITIONS

t

PZH

t

PZL

t

PLZ

t

PHZ

Open Closed Closed Open Closed Closed Closed Closed

Ω

5 k

SW2CL*

* Includes Jig and Probe Capacitance.

Figure 5

FAST AND LS TTL DATA

5-5