Datasheet SN74LS298D, SN74LS298DR2, SN74LS298ML1, SN74LS298ML2, SN74LS298N Datasheet (MOTOROLA)
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Semiconductor Components Industries, LLC, 1999
December, 1999 – Rev. 6
1 Publication Order Number:
SN74LS298/D
SN74LS298
Quad 2-Input Multiplexer
with Storage
The SN74LS298 is a Quad 2-Port Register. It is the logical
equivalent of a quad 2-input multiplexer followed by a quad 4-bit
edge-triggered register. A Common Select input selects between two
4-bit input ports (data sources.) The selected data is transferred to the
output register synchronous with the HIGH to LOW transition of the
Clock input.
The LS298 is fabricated with the Schottky barrier process for high
speed and is completely compatible with all ON Semiconductor TTL
families.
• Select From Two Data Sources
• Fully Edge-Triggered Operation
• Typical Power Dissipation of 65 mW
• Input Clamp Diodes Limit High Speed Termination Effects
GUARANTEED OPERATING RANGES
Symbol Parameter Min Typ Max Unit
V
CC
Supply Voltage 4.75 5.0 5.25 V
T
A
Operating Ambient
T emperature Range
0 25 70 °C
I
OH
Output Current – High –0.4 mA
I
OL
Output Current – Low 8.0 mA
LOW
POWER
SCHOTTKY
Device Package Shipping
ORDERING INFORMATION
SN74LS298N 16 Pin DIP 2000 Units/Box
SN74LS298D 16 Pin
SOIC
D SUFFIX
CASE 751B
http://onsemi.com
2500/Tape & Reel
PLASTIC
N SUFFIX
CASE 648
16
1
16
1
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CONNECTION DIAGRAM DIP (TOP VIEW)
Common Select Input
Clock (Active LOW Going Edge) Input
Data Inputs from Source 0
Data Inputs from Source 1
Register Outputs
S
CP
I0a – I
0d
I1a – I
1d
Qa – Q
d
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
10 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
5 U.L.
NOTES:
a) 1 TTL Unit Load (U.L.) = 40 mA HIGH/1.6 mA LOW.
HIGH LOW
(Note a)LOADING
PIN NAMES
LOGIC SYMBOL
NOTE:
The Flatpak version has the same
pinouts (Connection Diagram) as
the Dual In-Line Package.
14 13 12 11 10 9
123456
7
16 15
8
V
CC
I
1b
QaQbQcQ
d
SCP I
0c
I1aI
0aI0bI1cI1dI0d
GND
VCC = PIN 16
GND = PIN 8
324195 76
15 14 13 12
10
11
I
0aI1aI0bI1bI0cI1cI0dI1d
S
CP
Q
a
Q
b
Q
c
Q
d
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LOGIC OR BLOCK DIAGRAM
S
I
1a
I
0a
I
1b
I
0b
I
1c
I
0c
I
1d
I
0d
CP
R
CP
SQ
a
R
CP
SQ
b
Q
a
Q
b
Q
c
Q
d
14
12 673 4 5 9
11
12
10
1315
VCC = PIN 16
GND = PIN 8
= PIN NUMBERS
R
CP
SQ
c
R
CP
SQ
d
FUNCTIONAL DESCRIPTION
The LS298 is a high speed Quad 2-Port Register. It selects
four bits of data from two sources (ports)under the control
of a Common Select Input (S). The selected data is
transferred to the 4-bit output register synchronous with the
HIGH to LOW transition of the Clock input (CP
). The 4-bit
output register is fully edge-triggered. The Data inputs (I)
and Select input (S) must be stable only one setup time prior
to the HIGH to LOW transition of the clock for predictable
operation.
TRUTH TABLE
INPUTS OUTPUT
S I
0
I
1
Q
I I X L
I h X H
h X I L
h X h H
L = LOW Voltage Level
H = HIGH Voltage Level
X = Don’t Care
I = LOW Voltage Level one setup time prior to the HIGH to LOW clock transition.
h = HIGH Voltage Level one setup time prior to the HIGH to LOW clock transition.
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DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits
Symbol Parameter
Min Typ Max
Unit Test Conditions
V
IH
Input HIGH Voltage 2.0 V
Guaranteed Input HIGH Voltage for
All Inputs
V
IL
Input LOW Voltage
0.8
V
Guaranteed Input LOW Voltage for
All Inputs
V
IK
Input Clamp Diode Voltage –0.65 –1.5 V VCC = MIN, IIN = –18 mA
V
OH
Output HIGH Voltage 2.7 3.5 V
VCC = MIN, IOH = MAX, VIN = V
IH
or VIL per Truth Table
p
0.25 0.4 V IOL = 4.0 mA
VCC = VCC MIN,
VOLOutput LOW Voltage
0.35 0.5 V IOL = 8.0 mA
V
IN
=
V
IL
or
V
IH
per Truth Table
p
20 µA VCC = MAX, VIN = 2.7 V
IIHInput HIGH Current
0.1 mA VCC = MAX, VIN = 7.0 V
I
IL
Input LOW Current –0.4 mA VCC = MAX, VIN = 0.4 V
I
OS
Short Circuit Current (Note 1) –20 –100 mA VCC = MAX
I
CC
Power Supply Current 21 mA VCC = MAX
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS (T
A
= 25°C, VCC = 5.0 V)
Limits
Symbol Parameter
Min Typ Max
Unit Test Conditions
t
PLH
Propagation Delay,
18 27 ns
VCC = 5.0 V,
PLH
t
PHL
gy
Clock to Output
21 32 ns
CC
CL = 15 pF
AC SET-UP REQUIREMENTS (T
A
= 25°C, VCC = 5.0 V)
Limits
Symbol Parameter
Min Typ Max
Unit Test Conditions
t
W
Clock Pulse Width 20 ns
t
s
Data Setup Time 15 ns
t
s
Select Setup Time 25 ns
VCC = 5.0 V
t
h
Data Hold Time 5.0 ns
t
h
Select Hold Time 0
DEFINITIONS OF TERMS
SETUP TIME (ts) — is defined as the minimum time
required for the correct logic level to be present at the logic
input prior to the clock transition from LOW to HIGH in
order to be recognized and transferred to the outputs.
HOLD TIME (t
h
) — is defined as the minimum time
following the clock transition from LOW to HIGH that the
logic level must be maintained at the input in order to ensure
continued recognition. A negative HOLD TIME indicates
that the correct logic level may be released prior to the clock
transition from LOW to HIGH and still be recognized.
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*The shaded areas indicate when the input is permitted to
*change for predictable output performance.
Figure 1. Figure 2.
I0 I1*
CP
Q
1.3 V 1.3 V
1.3 V1.3 V
1.3 V 1.3 V
1.3 V 1.3 V
1.3 V 1.3 V
t
s(L)
t
s(L)
t
h(L)
t
h(L) = 0
t
h(H)
t
h(H) = 0
t
s(H)
t
s(H)
t
W(L)
t
PHL
t
PLH
CP
Q
S*
Q = I
0
Q = I
1
AC WAVEFORMS
t
W(H)
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P ACKAGE DIMENSIONS
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
ISSUE R
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
–A–
B
F
C
S
H
G
D
J
L
M
16 PL
SEATING
18
916
K
PLANE
–T–
M
A
M
0.25 (0.010) T
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A 0.740 0.770 18.80 19.55
B 0.250 0.270 6.35 6.85
C 0.145 0.175 3.69 4.44
D 0.015 0.021 0.39 0.53
F 0.040 0.70 1.02 1.77
G 0.100 BSC 2.54 BSC
H 0.050 BSC 1.27 BSC
J 0.008 0.015 0.21 0.38
K 0.110 0.130 2.80 3.30
L 0.295 0.305 7.50 7.74
M 0 10 0 10
S 0.020 0.040 0.51 1.01
____
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P ACKAGE DIMENSIONS
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
18
16 9
SEATING
PLANE
F
J
M
R
X 45
_
G
8 PLP
–B–
–A–
M
0.25 (0.010) B
S
–T–
D
K
C
16 PL
S
B
M
0.25 (0.010) A
S
T
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A 9.80 10.00 0.386 0.393
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
F 0.40 1.25 0.016 0.049
G 1.27 BSC 0.050 BSC
J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009
M 0 7 0 7
P 5.80 6.20 0.229 0.244
R 0.25 0.50 0.010 0.019
____
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