Datasheet SN74ls298 Datasheet

QUAD 2-INPUT MULTIPLEXER WITH STORAGE

The SN54/74LS298 is a Quad 2-Port Register. It is the logical equivalent of a quad 2-input multiplexer followed by a quad 4-bit edge-triggered register. A Common Select input selects between two 4-bit input ports (data sources.) The selected data is transferred to the output register synchronous with the HIGH to LOW transition of the Clock input.

The LS298 is fabricated with the Schottky barrier process for high speed and is completely compatible with all Motorola TTL families.

• Select From Two Data Sources

• Fully Edge-Triggered Operation

• Typical Power Dissipation of 65 mW

• Input Clamp Diodes Limit High Speed Termination Effects

CONNECTION DIAGRAM DIP (TOP VIEW)

V

QaQbQcQ

CC

16 15

123456

I

1b

14 13 12 11 10 9

I1aI

0aI0bI1cI1dI0d

d

SCP

7

GND

I

0c

NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package.

8

SN54/74LS298

QUAD 2-INPUT MULTIPLEXER

WITH STORAGE

LOW POWER SCHOTTKY

J SUFFIX

CERAMIC

16

1

16

1

16

1

CASE 620-09

N SUFFIX

PLASTIC

CASE 648-08

D SUFFIX

SOIC

CASE 751B-03

PIN NAMES LOADING (Note a)

HIGH

S Common Select Input 0.5 U.L. 0.25 U.L. CP Clock (Active LOW Going Edge) Input 0.5 U.L. 0.25 U.L. I0a–I I1a–I Qa–Q

NOTES: a) 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW. b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial

(74) T emperature Ranges.

Data Inputs From Source 0 0.5 U.L. 0.25 U.L.

0d

Data Inputs From Source 1 0.5 U.L. 0.25 U.L.

1d

Register Outputs (Note b) 10 U.L. 5 (2.5) U.L.

d

LOW

FAST AND LS TTL DAT A

5-1

ORDERING INFORMATION

SN54LSXXXJ Ceramic SN74LSXXXN Plastic SN74LSXXXD SOIC

LOGIC SYMBOL

32 4195 76

I0aI1aI0bI1bI0cI1cI0dI

10

S

11

CP

Q

15 14 13 12

a

VCC = PIN 16 GND = PIN 8

Q

b

c

1d

Q

d

LOGIC OR BLOCK DIAGRAM

SN54/74LS298

VCC = PIN 16 GND = PIN 8

= PIN NUMBERS

CP

I

1a

S

10

11

I

0a

I

R CP SQ

I

1b

a

0b

12 673 4 59

Q

a

FUNCTIONAL DESCRIPTION

The LS298 is a high speed Quad 2-Port Register. It selects

four bits of data from two sources (ports)under the control of a Common Select Input (S). The selected data is transferred to the 4-bit output register synchronous with the HIGH to LOW

R CP SQ

I

b

14

1c

Q

b

I

0c

R CP SQ

c

1315

I

1d

Q

c

I

0d

transition of the Clock input (CP

R CP SQ

d

12

Q

d

). The 4-bit output register is fully edge-triggered. The Data inputs (I) and Select input (S) must be stable only one setup time prior to the HIGH to LOW transition of the clock for predictable operation.

TRUTH TABLE

INPUTS OUTPUT

S I

I I X L

I h X H h X I L h X h H

L = LOW Voltage Level H = HIGH Voltage Level X = Don’t Care I = LOW Voltage Level one setup time prior to the HIGH to LOW clock transition. h = HIGH Voltage Level one setup time prior to the HIGH to LOW clock transition.

0

I

1

Q

GUARANTEED OPERATING RANGES

Symbol Parameter Min Typ Max Unit

V

T

I

OH

I

OL

CC

A

Supply Voltage 54

74

Operating Ambient Temperature Range 54

74 Output Current — High 54, 74 –0.4 mA Output Current — Low 54

74

4.5

4.75 –55

0

5.0

5.0 25

25

5.5

5.25 125

70

4.0

8.0

V

°C

mA

FAST AND LS TTL DATA

5-2

SN54/74LS298

VILI

LOW Volt

V

pg

VOHOutput HIGH Volt

CC

,

OH

,

IN IH

VOLOutput LOW Volt

V

IIHI

HIGH C

t

PLH

pg y,

CC

,

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)

Limits

Symbol Parameter

V

IH

V

IK

I

IL

I

OS

I

CC

Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.

Input HIGH Voltage 2.0 V

nput

Input Clamp Diode Voltage –0.65 –1.5 V VCC = MIN, IIN = –18 mA

nput

Input LOW Current –0.4 mA VCC = MAX, VIN = 0.4 V Short Circuit Current (Note 1) –20 –100 mA VCC = MAX Power Supply Current 21 mA VCC = MAX

age

urren

54 74

54 2.5 3.5 V 74 2.7 3.5 V

54, 74 0.25 0.4 V IOL = 4.0 mA

74 0.35 0.5 V IOL = 8.0 mA

Min Typ Max

0.7

0.8

20 µA VCC = MAX, VIN = 2.7 V

0.1 mA VCC = MAX, VIN = 7.0 V

Unit Test Conditions

Guaranteed Input HIGH Voltage for All Inputs

Guaranteed Input LOW Voltage for All Inputs

VCC = MIN, IOH = MAX, VIN = V or VIL per Truth Table

IH

VCC = VCC MIN,

=

or

IN

IL

per Truth Table

IH

AC CHARACTERISTICS (T

Symbol Parameter

t

PLH

t

PHL

Propagation Delay, Clock to Output

AC SET-UP REQUIREMENTS (T

Symbol Parameter

t

W

t

s

t

s

t

h

t

h

Clock Pulse Width 20 ns Data Setup Time 15 ns Select Setup Time 25 ns Data Hold Time 5.0 ns Select Hold Time 0

= 25°C, VCC = 5.0 V)

A

= 25°C, VCC = 5.0 V)

A

Min Typ Max

DEFINITIONS OF TERMS

SETUP TIME (ts) — is defined as the minimum time required for the correct logic level to be present at the logic input prior to the clock transition from LOW to HIGH in order to be recognized and transferred to the outputs.

HOLD TIME (th) — is defined as the minimum time following

Limits

Unit Test Conditions

18 27 ns 21 32 ns

Limits

Unit Test Conditions

VCC = 5.0 V,

CL = 15 pF

VCC = 5.0 V

the clock transition from LOW to HIGH that the logic level must be maintained at the input in order to ensure continued recognition. A negative HOLD TIME indicates that the correct logic level may be released prior to the clock transition from LOW to HIGH and still be recognized.

FAST AND LS TTL DATA

5-3

SN54/74LS298

AC WAVEFORMS

I0 I1*

CP

1.3 V 1.3 V t

t

s(L)

Q

h(L)

t

W(L)

t

W(H)

t

PHLtPLH

1.3 V 1.3 V

t

h(H)

t

s(H)

1.3 V1.3 V

*The shaded areas indicate when the input is permitted to

*change for predictable output performance.

S*

1.3 V 1.3 V t

t

s(L)

1.3 V 1.3 V

CP

Q

h(L) = 0

Q = I

0

t

h(H) = 0

t

s(H)

Q = I

1

Figure 1 Figure 2

FAST AND LS TTL DATA

5-4