Datasheet SN74LS283D, SN74LS283DR2, SN74LS283MEL, SN74LS283ML1, SN74LS283ML2 Datasheet (MOTOROLA)

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Semiconductor Components Industries, LLC, 1999
December, 1999 – Rev. 6
1 Publication Order Number:
SN74LS283/D
SN74LS283
4-Bit Binary Full Adder with Fast Carry
The SN74LS283 is a high-speed 4-Bit Binary Full Adder with
internal carry lookahead. It accepts two 4-bit binary words (A1–A
4,
B1–B4) and a Carry Input (C0). It generates the binary Sum outputs (1–4) and the Carry Output (C4) from the most significant bit. The LS283 operates with either active HIGH or active LOW operands (positive or negative logic).
GUARANTEED OPERATING RANGES
Symbol Parameter Min Typ Max Unit
V
CC
Supply Voltage 4.75 5.0 5.25 V
T
A
Operating Ambient
T emperature Range
0 25 70 °C
I
OH
Output Current – High –0.4 mA
I
OL
Output Current – Low 8.0 mA
LOW
POWER
SCHOTTKY
Device Package Shipping
ORDERING INFORMATION
SN74LS283N 16 Pin DIP 2000 Units/Box SN74LS283D 16 Pin
SOIC
D SUFFIX
CASE 751B
http://onsemi.com
2500/Tape & Reel
PLASTIC N SUFFIX CASE 648
16
1
16
1
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CONNECTION DIAGRAM DIP (TOP VIEW)
Operand A Inputs Operand B Inputs Carry Input Sum Outputs Carry Output
A
1
– A
4
B1 – B
4
C
0
S1 –
S
4
C
4
1.0 U.L.
1.0 U.L.
0.5 U.L. 10 U.L. 10 U.L.
0.5 U.L.
0.5 U.L.
0.25 U.L. 5 U.L. 5 U.L.
NOTES:
a) 1 TTL Unit Load (U.L.) = 40 mA HIGH/1.6 mA LOW.
HIGH LOW
(Note a)LOADING
PIN NAMES
LOGIC SYMBOL
NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package.
5 3 14 12 6 2 15 11
97
4 1 13 10
A
1A2A3A4B1B2B3B4
∑1∑2∑3∑
4
VCC = PIN 16 GND = PIN 8
C
0
C
4
14 13 12 11 10 9
123456
7
16 15
8
V
CC
Σ
2
B3A3Σ3A
4
Σ
4
B
4
C
4
B2A2Σ1A1B1C0GND
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LOGIC DIAGRAM
C0A
1
B
1
A
2
B
2
A
3
B
3
A
4
B
4
1
2
3
4
C
4
VCC = PIN 16 GND = PIN 8
= PIN NUMBERS
C
1
C
2
C
3
14
1
267
3
4
5
9
11
12
10
13
15
FUNCTIONAL DESCRIPTION
The LS283 adds two 4-bit binary words (A plus B) plus
the incoming carry. The binary sum appears on the sum outputs (
1–4
) and outgoing carry (C4) outputs.
C0 + (A
1
+ B1) + 2(A
2
+ B2) + 4(A
3
+ B3) + 8(A
4
+ B4) =
1
+ 2
2
+ 4 3 + 8
4
+ 16C
4
Where: (+) = plus
Due to the symmetry of the binary add function the LS283 can be used with either all inputs and outputs active HIGH (positive logic) or with all inputs and outputs active LOW (negative logic). Note that with active HIGH inputs, Carry Input can not be left open, but must be held LOW when no carry in is intended.
Example:
C0A1A2A3A4B1B2B3B4∑1∑2∑3∑4C
4
logic levels L L H L H H L L H H H L L H
Active HIGH 0 0 1 0 1 1 0 0 1 1 1 0 0 1 (10+9=19)
Active LOW 1 1 0 1 0 0 1 1 0 0 0 1 1 0 (carry+5+6=12)
Interchanging inputs of equal weight does not affect the operation, thus C0, A1, B1, can be arbitrarily assigned to pins 7, 5 or 3.
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FUNCTIONAL TRUTH TABLE
C (n–1) A
n
B
n
n
C
n
L L L L L L L H H L L H L H L L H H L H H L L H L H L H L H H H L L H H H H H H
C1–C
3
are generated internally
C
0
is an external input
C
4
is an output generated internally
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits
Symbol Parameter
Min Typ Max
Unit Test Conditions
V
IH
Input HIGH Voltage 2.0 V
Guaranteed Input HIGH Voltage for All Inputs
V
IL
Input LOW Voltage
0.8 V
Guaranteed Input LOW Voltage for All Inputs
V
IK
Input Clamp Diode Voltage –0.65 –1.5 V VCC = MIN, IIN = –18 mA
V
OH
Output HIGH Voltage 2.7 3.5 V
VCC = MIN, IOH = MAX, VIN = V
IH
or VIL per Truth Table
p
0.25 0.4 V IOL = 4.0 mA
VCC = VCC MIN,
VOLOutput LOW Voltage
0.35 0.5 V IOL = 8.0 mA
V
IN
=
V
IL
or
V
IH
per Truth Table
C
0
20 µA
p
Any A or B 40 µA
V
CC
=
MAX, V
IN
= 2.7
V
IIHInput HIGH Current
C
0
0.1 mA
Any A or B 0.2 mA
V
CC
=
MAX, V
IN
= 7.0
V
p
C
0
–0.4 mA
IILInput LOW Current
Any A or B –0.8 mA
V
CC
=
MAX, V
IN
= 0.4
V
I
OS
Short Circuit Current (Note 1) –20 –100 mA VCC = MAX
I
CC
Power Supply Current
Total, Output HIGH
34
mA VCC = MAX
CC
Total, Output LOW 39
CC
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
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AC CHARACTERISTICS (T
A
= 25°C, VCC = 5.0 V)
Limits
Symbol Parameter
Min Typ Max
Unit Test Conditions
t
PLH
t
PHL
Propagation Delay, C0 Input to Any Σ Output
16 15
24 24
ns
t
PLH
t
PHL
Propagation Delay, Any A or B Input to Σ Outputs
15 15
24 24
ns
CL = 15 pF
t
PLH
t
PHL
Propagation Delay, C0 Input to C
4
Output
11 11
17 22
ns
L
Figures 1 & 2
t
PLH
t
PHL
Propagation Delay, Any A or B Input to C
4
Output
11
12
17 17
ns
Figure 1. Figure 2.
V
IN
V
OUT
1.3 V
1.3 V
1.3 V
1.3 V
V
IN
V
OUT
t
PHL
t
PLH
t
PLH
t
PHL
AC WAVEFORMS
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P ACKAGE DIMENSIONS
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
ISSUE R
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
–A–
B
F
C
S
H
G
D
J
L
M
16 PL
SEATING
18
916
K
PLANE
–T–
M
A
M
0.25 (0.010) T
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A 0.740 0.770 18.80 19.55 B 0.250 0.270 6.35 6.85 C 0.145 0.175 3.69 4.44 D 0.015 0.021 0.39 0.53 F 0.040 0.70 1.02 1.77 G 0.100 BSC 2.54 BSC H 0.050 BSC 1.27 BSC J 0.008 0.015 0.21 0.38 K 0.110 0.130 2.80 3.30 L 0.295 0.305 7.50 7.74 M 0 10 0 10 S 0.020 0.040 0.51 1.01
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P ACKAGE DIMENSIONS
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.
18
16 9
SEATING
PLANE
F
J
M
R
X 45
_
G
8 PLP
–B–
–A–
M
0.25 (0.010) B
S
–T–
D
K
C
16 PL
S
B
M
0.25 (0.010) A
S
T
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A 9.80 10.00 0.386 0.393 B 3.80 4.00 0.150 0.157 C 1.35 1.75 0.054 0.068 D 0.35 0.49 0.014 0.019
F 0.40 1.25 0.016 0.049
G 1.27 BSC 0.050 BSC
J 0.19 0.25 0.008 0.009 K 0.10 0.25 0.004 0.009 M 0 7 0 7
P 5.80 6.20 0.229 0.244
R 0.25 0.50 0.010 0.019
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