Page 1
9-BIT ODD/EVEN PARITY
GENERATORS/CHECKERS
The SN54/74LS280 is a Universal 9-Bit Parity Generator/Checker. It features odd/even outputs to facilitate either odd or even parity. By cascading,
the word length is easily expanded.
The LS280 is designed without the expander input implementation, but the
corresponding function is provided by an input at Pin 4 and the absence of any
connection at Pin 3. This design permits the LS280 to be substituted for the
LS180 which results in improved performance. The LS280 has buffered
inputs to lower the drive requirements to one LS unit load.
• Generates Either Odd or Even Parity for Nine Data Lines
• Typical Data-to-Output Delay of only 33 ns
• Cascadable for n-Bits
• Can Be Used To Upgrade Systems Using MSI Parity Circuits
• Typical Power Dissipation = 80 mW
INPUTS
SN54/74LS280
9-BIT ODD/EVEN PARITY
GENERATORS/CHECKERS
LOW POWER SCHOTTKY
J SUFFIX
CERAMIC
14
1
CASE 632-08
VCCFEDCBA
14 13 12 11 10 9
FEDCB
HI
123456
G H NC I
INPUTS
INPUT
∑
EVEN∑ODD
∑
EVEN
OUTPUTS
∑
ODD
8
AG
7
GND
14
1
14
1
N SUFFIX
PLASTIC
CASE 646-06
D SUFFIX
SOIC
CASE 751A-02
ORDERING INFORMATION
FUNCTION TABLE
NUMBER OF INPUTS A
THRU 1 THAT ARE HIGH
0, 2, 4, 6, 8 H L
1, 3, 5, 7, 9 L H
H = HIGH Level, L = LOW Level
OUTPUTS
∑EVEN ∑ODD
SN54LSXXXJ Ceramic
SN74LSXXXN Plastic
SN74LSXXXD SOIC
GUARANTEED OPERATING RANGES
Symbol Parameter Min Typ Max Unit
V
T
I
I
CC
A
OH
OL
Supply Voltage 54
74
Operating Ambient Temperature Range 54
74
Output Current — High 54, 74 –0.4 mA
Output Current — Low 54
74
4.5
4.75
–55
0
5.0
5.0
25
25
5.5
5.25
125
70
4.0
8.0
V
°C
mA
FAST AND LS TTL DAT A
5-1
Page 2
FUNCTIONAL BLOCK DIAGRAM
VILI
LOW Volt
V
pg
VOHOutput HIGH Volt
CC
,
OH
,
IN IH
VOLOutput LOW Volt
V
V
V
IIHI
HIGH C
t
C
F
(8)
A
(9)
B
(10)
C
(11)
D
(12)
E
(13)
F
(1)
G
(2)
H
(4)
I
SN54/74LS280
(5)
(6)
∑
EVEN
∑
ODD
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE
Limits
Symbol Parameter
V
IH
V
IK
I
IL
I
OS
I
CC
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS (T
Symbol Parameter
t
PLH
t
PHL
t
PLH
t
PHL
Input HIGH Voltage 2.0 V
nput
Input Clamp Diode Voltage –0.65 –1.5 V VCC = MIN, IIN = –18 mA
nput
Input LOW Current –0.4 mA VCC = MAX, VIN = 0.4 V
Short Circuit Current (Note 1) –20 –100 mA VCC = MAX
Power Supply Current 27 mA VCC = MAX
Propagation Delay, Data to Output
Propagation Delay, Data to Output
age
age
age
urren
= 25°C, VCC = 5.0 V)
A
ΣEVEN
ΣODD
54
74
54 2.5 3.5 V
74 2.7 3.5 V
54, 74 0.25 0.4 V IOL = 4.0 mA
74 0.35 0.5 V IOL = 8.0 mA
Min Typ Max
0.7
0.8
20 µA VCC = MAX, VIN = 2.7 V
0.1 mA VCC = MAX, VIN = 7.0 V
Limits
Min Typ Max
33
29
23
31
50
45
35
50
(unless otherwise specified)
Unit Test Conditions
Guaranteed Input HIGH Voltage for
All Inputs
Guaranteed Input LOW Voltage for
All Inputs
VCC = MIN, IOH = MAX, VIN = V
or VIL per Truth Table
VCC = VCC MIN,
IN
per Truth Table
Unit Test Conditions
ns
= 15 p
L
ns
=
IH
or
IL
IH
FAST AND LS TTL DATA
5-2
Loading...