Datasheet SN74LS259D, SN74LS259DR2, SN74LS259M, SN74LS259MEL, SN74LS259ML1 Datasheet (MOTOROLA)
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Semiconductor Components Industries, LLC, 1999
December, 1999 – Rev. 6
1 Publication Order Number:
SN74LS259/D
SN74LS259
8-Bit Addressable Latch
The SN74LS259 is a high-speed 8-Bit Addressable Latch designed
for general purpose storage applications in digital systems. It is a
multifunctional device capable of storing single line data in eight
addressable latches, and also a 1-of-8 decoder and demultiplexer with
active HIGH outputs. The device also incorporates an active LOW
common Clear for resetting all latches, as well as, an active LOW
Enable.
• Serial-to-Parallel Conversion
• Eight Bits of Storage With Output of Each Bit Available
• Random (Addressable) Data Entry
• Active High Demultiplexing or Decoding Capability
• Easily Expandable
• Common Clear
GUARANTEED OPERATING RANGES
Symbol Parameter Min Typ Max Unit
V
CC
Supply Voltage 4.75 5.0 5.25 V
T
A
Operating Ambient
T emperature Range
0 25 70 °C
I
OH
Output Current – High –0.4 mA
I
OL
Output Current – Low 8.0 mA
LOW
POWER
SCHOTTKY
Device Package Shipping
ORDERING INFORMATION
SN74LS259N 16 Pin DIP 2000 Units/Box
SN74LS259D 16 Pin
SOIC
D SUFFIX
CASE 751B
http://onsemi.com
2500/Tape & Reel
PLASTIC
N SUFFIX
CASE 648
16
1
16
1
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CONNECTION DIAGRAM DIP (TOP VIEW)
Address Inputs
Data Input
Enable (Active LOW) Input
Clear (Active LOW) Input
Parallel Latch Outputs
A
0
, A1, A
2
D
E
C
Q0 – Q
7
0.5 U.L.
0.5 U.L.
1.0 U.L.
0.5 U.L.
10 U.L.
0.25 U.L.
0.25 U.L.
0.5 U.L.
0.25 U.L.
5 U.L.
NOTES:
a) 1 TTL Unit Load (U.L.) = 40 mA HIGH/1.6 mA LOW.
HIGH LOW
(Note a)LOADING
PIN NAMES
14 13 12 11 10 9
123456
7
16 15
8
V
CC
A
o
C E DQ
7
Q
5
Q
6
Q
4
A1A2Q0Q1Q2Q3GND
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E
C MODE
L
H
L
H
H
H
L
L
Addressable Latch
Memory
Active HIGH Eight-Channel
Demultiplexer
Clear
MODE SELECTION
X = Don’t Care Condition
L = LOW Voltage Level
H = HIGH Voltage Level
Q
N–1
= Previous Output State
SN74LS259
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LOGIC DIAGRAM
E DA
0
A1A
2
C
Q
0
Q
1
Q
2
Q
3
Q
4
Q
5
Q
6
Q
7
14 12
67
3
4 5 9 11 1210
13 15
VCC = PIN 16
GND = PIN 8
= PIN NUMBERS
FUNCTIONAL DESCRIPTION
The SN74LS259 has four modes of operation as shown in
the mode selection table. In the addressable latch mode, data
on the Data line (D) is written into the addressed latch.The
addressed latch will follow the data input with all
non-addressed latches remaining in their previous states. In
the memory mode, all latches remain in their previous state
and are unaffected by the Data or Address inputs.
In the one-of-eight decoding or demultiplexing mode, the
addressed output will follow the state of the D input with all
other inputs in the LOW state. In the clear mode all outputs
are LOW and unaffected by the address and data inputs.
When operating the SN74LS259 as an addressable latch,
changing more then one bit of the address could impose a
transient wrong address. Therefore, this should only be done
while in the memory mode.
The truth table below summarizes the operations.
TRUTH TABLE
PRESENT OUTPUT STATES
C E D A0A1A2Q
0
Q
1
Q
2
Q
3
Q4Q
5
Q
6
Q
7
MODE
L H X X X X L L L L L L L L Clear
L LL L L L L L L L L L L L Demultiplex
L LH L L L H LLLLLLL
L LL H L L L LLLLLLL
L LH H L L L HLLLLLL
• •• • •
• •• • •
• •• • •
• •• • •
• •• • •
L LH H H H L LLLLLLH
H H X X X X Q
N–1
Memory
H I I L L L L Q
N–1QN–1QN–1
Addressable
H LH L L L H Q
N–1QN–1
Latch
H LL H L L Q
N–1
LQ
N–1
H LH H L L Q
N–1
HQ
N–1
• •• • •
• •• • •
• •• • •
• •• • •
• •• • •
H LL H H H Q
N–1
Q
N–1
L
H L H H H H Q
N–1
Q
N–1
H
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DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits
Symbol Parameter
Min Typ Max
Unit Test Conditions
V
IH
Input HIGH Voltage 2.0 V
Guaranteed Input HIGH Voltage for
All Inputs
V
IL
Input LOW Voltage
0.8
V
Guaranteed Input LOW Voltage for
All Inputs
V
IK
Input Clamp Diode Voltage –0.65 –1.5 V VCC = MIN, IIN = –18 mA
V
OH
Output HIGH Voltage 2.7 3.5 V
VCC = MIN, IOH = MAX, VIN = V
IH
or VIL per Truth Table
p
0.25 0.4 V IOL = 4.0 mA
VCC = VCC MIN,
VOLOutput LOW Voltage
0.35 0.5 V IOL = 8.0 mA
V
IN
=
V
IL
or
V
IH
per Truth Table
p
20 µA VCC = MAX, VIN = 2.7 V
IIHInput HIGH Current
0.1 mA VCC = MAX, VIN = 7.0 V
I
IL
Input LOW Current –0.4 mA VCC = MAX, VIN = 0.4 V
I
OS
Short Circuit Current (Note 1) –20 –100 mA VCC = MAX
I
CC
Power Supply Current 36 mA VCC = MAX
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS (T
A
= 25°C, VCC = 5.0 V)
Limits
Symbol Parameter
Min Typ Max
Unit Test Conditions
t
PLH
t
PHL
Turn-Off Delay, Enable to Output
Turn-On Delay, Enable to Output
22
15
35
24
ns
ns
t
PLH
t
PHL
Turn-Off Delay, Data to Output
Turn-On Delay, Data to Output
20
13
32
21
ns
ns
CL = 15 pF
t
PLH
t
PHL
Turn-Off Delay, Address to Output
Turn-On Delay, Address to Output
24
18
38
29
ns
ns
L
t
PHL
Turn-On Delay, Clear to Output 17 27 ns
AC SET-UP REQUIREMENTS (T
A
= 25°C, VCC = 5.0 V)
Limits
Symbol Parameter
Min Typ Max
Unit
t
s
Input Setup Time 20 ns
t
W
Pulse Width, Clear or Enable 15 ns
t
h
Hold Time, Data 5.0 ns
t
h
Hold Time, Address 20 ns
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t
s
Figure 1. Turn-on and Turn-off Delays, Enable To
Output and Enable Pulse Width
Figure 2. Turn-on and Turn-off Delays,
Data to Output
Figure 3. Turn-on and Turn-off Delays,
Address to Output
NOTES:
1. The Address to Enable Setup Time is the time before the HIGH-to-LOW Enable transition that the Address must be stable so that the correct latch is
addressed and the other latches are not affected.
2. The shaded areas indicate when the inputs are permitted to change for predictable output performance.
OTHER CONDITIONS: C = H, A = STABLE
OTHER CONDITIONS: E
= L, C = H, A = STABLE
OTHER CONDITIONS: E
= L, C = L, D = H
OTHER CONDITIONS: C
= H, A = STABLE
OTHER CONDITIONS: E = H
1.3 V
t
PHL
t
PLH
1.3 V
D
E
Q
1.3 V 1.3 V
1.3 V1.3 V
t
PLH
t
PHL
D
Q
1.3 V
1.3 V
t
PHL
C
Q
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V 1.3 V
A
1
A
1
Q
1
t
PLH
D
E
Q
th(H) th(L)
1.3 V
OTHER CONDITIONS: C
= H
STABLE ADDRESS
A
E
ts(H)
ts(L)
t
PHL
t
w
t
w
Q=D Q=D
AC WAVEFORMS
Figure 4. Setup and Hold Time, Data to Enable
Figure 5. Turn-on Delay, Clear to Output
Figure 6. Setup Time, Address to Enable
(See Notes 1 and 2)
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P ACKAGE DIMENSIONS
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
ISSUE R
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
–A–
B
F
C
S
H
G
D
J
L
M
16 PL
SEATING
18
916
K
PLANE
–T–
M
A
M
0.25 (0.010) T
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A 0.740 0.770 18.80 19.55
B 0.250 0.270 6.35 6.85
C 0.145 0.175 3.69 4.44
D 0.015 0.021 0.39 0.53
F 0.040 0.70 1.02 1.77
G 0.100 BSC 2.54 BSC
H 0.050 BSC 1.27 BSC
J 0.008 0.015 0.21 0.38
K 0.110 0.130 2.80 3.30
L 0.295 0.305 7.50 7.74
M 0 10 0 10
S 0.020 0.040 0.51 1.01
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P ACKAGE DIMENSIONS
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
18
16 9
SEATING
PLANE
F
J
M
R
X 45
_
G
8 PLP
–B–
–A–
M
0.25 (0.010) B
S
–T–
D
K
C
16 PL
S
B
M
0.25 (0.010) A
S
T
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A 9.80 10.00 0.386 0.393
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
F 0.40 1.25 0.016 0.049
G 1.27 BSC 0.050 BSC
J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009
M 0 7 0 7
P 5.80 6.20 0.229 0.244
R 0.25 0.50 0.010 0.019
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