Page 1
DUAL 4-BIT
ADDRESSABLE LATCH
The SN54/74LS256 is a Dual 4-Bit Addressable Latch with common control
inputs; these include two Address inputs (A0, A1), an active LOW Enable input
(E) and an active LOW Clear input (CL). Each latch has a Data input (D) and
four outputs (Q0–Q3).
When the Enable (E
(Q0–Q3) are LOW. Dual 4-channel demultiplexing occurs when the (CL
E
are both LOW. When CL is HIGH and E is LOW, the selected output
(Q0–Q3), determined by the Address inputs, follows D. When the E
HIGH, the contents of the latch are stored. When operating in the addressable
latch mode (E
=LOW, CL=HIGH), changing more than one bit of the Address
(A0, A1) could impose a transient wrong address. Therefore, this should be
done only while in the memory mode (E
• Serial-to-Parallel Capability
• Output From Each Storage Bit Available
• Random (Addressable) Data Entry
• Easily Expandable
• Active Low Common Clear
• Input Clamp Diodes Limit High Speed Termination Effects
) is HIGH and the Clear input (CL) is LOW, all outputs
) and
goes
=CL=HIGH).
SN54/74LS256
DUAL 4-BIT
ADDRESSABLE LA TCH
LOW POWER SCHOTTKY
J SUFFIX
CERAMIC
16
1
16
1
CASE 620-09
N SUFFIX
PLASTIC
CASE 648-08
CONNECTION DIAGRAM DIP (TOP VIEW)
V
CC
16 15
123456
A
0
PIN NAMES LOADING (Note a)
A0, A
1
Da, D
b
E Enable Input (Active LOW) 1.0 U.L. 0.5 U.L.
CL Clear Input (Active LOW) 0.5 U.L. 0.25 U.L.
Q0a–Q3a,
Q0b–Q
NOTES:
a) 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.
b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial
3b
(74) T emperature Ranges.
E DbQ
CL
14 13 12 11 10 9
A1DaQ0aQ1aQ2aQ3aGND
Address Inputs 0.5 U.L. 0.25 U.L.
Data Inputs 0.5 U.L. 0.25 U.L.
Parallel Latch Outputs (Note b) 10 U.L. 5 (2.5) U.L.
3b
Q
Q
2b
Q
1b
7
0b
NOTE:
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual In-Line Package.
8
HIGH
LOW
D SUFFIX
16
1
SOIC
CASE 751B-03
ORDERING INFORMATION
SN54LSXXXJ Ceramic
SN74LSXXXN Plastic
SN74LSXXXD SOIC
LOGIC SYMBOL
321151413
D
E
a
Q0aQ1aQ2aQ
A
0
A
1
CL
3a
ED
A
0
A
1
CL
Q0bQ1bQ2bQ
b
3b
FAST AND LS TTL DAT A
5-1
4567 9101112
VCC = PIN 16
GND = PIN 8
Page 2
LOGIC DIAGRAM
SN54/74LS256
E D
14 12
VCC = PIN 16
GND = PIN 8
a
3
4 5 9 11 1210
Q
0a
= PIN NUMBERS
A
0
Q
1a
A
1
67
Q
2a
CL D
1315
Q
3a
b
Q
0b
TRUTH TABLE
CL E D A
L H X X X L L L L Clear
L L L L L L L L L Demultiplex
L LHLLHLLL
LLLHLLLLL
LLHHLLHLL
LLLLHLLLL
LLHLHLLHL
LLLHHLLLL
LLHHHLLLH
HHXXXQ
H L L L L L Q
H LHLLHQ
H LLHLQ
H LHHLQ
H LLLHQ
H LHLHQ
H LLHHQ
H L H H H Q
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
0
A
Q
1
N–1
N–1
N–1
N–1
N–1
N–1
N–1
Q
0
Q
N–1
N–1
N–1
LQ
HQ
Q
N–1
Q
N–1
Q
N–1
Q
N–1
MODE SELECTION
E CL MODE
L H Addressable Latch
H H Memory
L L Dual 4-Channel Demultiplexer
H L Clear
Q
1b
Q
1
2
Q
N–1
Q
N–1
Q
N–1
N–1
N–1
LQ
HQ
Q
N–1
Q
N–1
Q
2b
Q
3
Q
N–1
Q
N–1
Q
N–1
Q
N–1
Q
N–1
N–1
N–1
L
H
MODE
Memory
Addressable
Latch
Q
3b
FAST AND LS TTL DATA
5-2
Page 3
SN54/74LS256
VILI
LOW Volt
V
pg
VOLOutput LOW Volt
V
V
V
I
IH
C
F
GUARANTEED OPERATING RANGES
Symbol Parameter Min Typ Max Unit
V
CC
T
A
I
OH
I
OL
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Symbol Parameter
V
IH
V
IK
V
OH
I
IH
I
IL
I
OS
I
CC
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
Supply Voltage 54
Operating Ambient Temperature Range 54
Output Current — High 54, 74 –0.4 mA
Output Current — Low 54
Limits
Min Typ Max
Input HIGH Voltage 2.0 V
nput
Input Clamp Diode Voltage –0.65 –1.5 V VCC = MIN, IIN = –18 mA
Output HIGH Voltage 54, 74 2.4 3.5 V
Input HIGH Current
Others
E
Input
Others
E
Input
Input LOW Current
Others
E
Input
Short Circuit Current (Note 1) –20 –100 mA VCC = MAX
Power Supply Current 30 mA VCC = MAX
age
age
54
74
54, 74 0.25 0.4 V IOL = 4.0 mA
74 0.35 0.5 V IOL = 8.0 mA
74
74
74
0.7
0.8
20
40
0.1
0.2
–0.4
–0.8
4.5
4.75
–55
0
Unit Test Conditions
Guaranteed Input HIGH Voltage for
All Inputs
Guaranteed Input LOW Voltage for
All Inputs
VCC = MIN, IOH = MAX, VIN = V
or VIL per Truth Table
µA VCC = MAX, VIN = 2.7 V
mA VCC = MAX, VIN = 7.0 V
mA VCC = MAX, VIN = 0.4 V
5.0
5.0
25
25
5.5
5.25
125
70
4.0
8.0
VCC = VCC MIN,
=
IN
IL
per Truth Table
or
IH
IH
V
°C
mA
AC CHARACTERISTICS (T
Symbol Parameter
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PHL
Turn-Off Delay, Enable to Output
Turn-On Delay, Enable to Output
Turn-Off Delay, Data to Output
Turn-On Delay, Data to Output
Turn-Off Delay, Address to Output
Turn-On Delay, Address to Output
Turn-On Delay, Clear to Output 12 23 ns Figure 5
A
= 25°C)
Limits
Min Typ Max
20
16
20
13
20
14
27
24
30
20
30
24
FAST AND LS TTL DATA
5-3
Unit Test Conditions
ns
ns
ns
ns
ns
ns
Figure 1
Figure 2
Figure 3
VCC = 5.0 V,
L
= 15 p
Page 4
SN54/74LS256
Fi
6
AC SET-UP REQUIREMENTS (T
Symbol Parameter
t
s
t
s
t
h
t
h
t
W
D
E
Q
Data Setup Time 20 ns
Address Setup Time 0 ns
Data Hold Time 0 ns Figure 4
Address Hold Time 15 ns Figure 6
Enable Pulse Width 15 ns Figure 1
t
pw
t
PHL
OTHER CONDITIONS: CL = H, A = STABLE
= 25°C)
A
t
PLH
t
pw
1.3 V
Figure 1. T urn-on and Turn-off Delays, Enable To
Output and Enable Pulse Width
Limits
Min Typ Max
AC WAVEFORMS
1.3 V
Unit Test Conditions
D
Q
OTHER CONDITIONS: E
Figure 2. T urn-on and Turn-off Delays,
gures 4 &
VCC = 5.0 V
1.3 V 1.3 V
t
PHL
= L, CL = H, A = STABLE
Data to Output
1.3 V1.3 V
t
PLH
A
1
A
1
Q
1
OTHER CONDITIONS: E
Figure 3. T urn-on and Turn-off Delays,
1.3 V
1.3 V
1.3 V
1.3 V
t
PHL
1.3 V 1.3 V
= L, CL = L, D = H
t
PLH
D
E
Q
ts(H)
Q=D Q=D
OTHER CONDITIONS: C
th(H) th(L)
= H, A = STABLE
ts(L)
Figure 4. Setup and Hold Time, Data to Enable
Address to Output
C
Q
OTHER CONDITIONS: E
= H
Figure 5. Turn-on Delay, Clear to Output
1.3 V
t
PHL
1.3 V
1.3 V
A
E
OTHER CONDITIONS: CL
t
s
= H
STABLE ADDRESS
1.3 V
Figure 6. Setup Time, Address to Enable
t
h
(See Notes 1 and 2)
NOTES:
1. The Address to Enable Setup Time is the time before the HIGH-to-LOW Enable transition that the Address must be stable so that the correct latch is
addressed and the other latches are not affected.
2. The shaded areas indicate when the inputs are permitted to change for predictable output performance.
1.3 V
FAST AND LS TTL DATA
5-4
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