Datasheet SN74ls253 Datasheet

DUAL 4-INPUT MULTIPLEXER
WITH 3-STATE OUTPUTS

The LSTTL/MSI SN54/74LS253 is a Dual 4-Input Multiplexer with 3-state
outputs. It can select two bits of data from four sources using common select
inputs. The outputs may be individually switched to a high impedance state
with a HIGH on the respective Output Enable (E
to interface directly with bus oriented systems. It is fabricated with the
Schottky barrier diode process for high speed and is completely compatible
with all Motorola TTL families.

• Schottky Process for High Speed

• Multifunction Capability

• Non-Inverting 3-State Outputs

• Input Clamp Diodes Limit High Speed Termination Effects

CONNECTION DIAGRAM DIP (TOP VIEW)

E

V

0bS0I3bI2b

CC

16 15

14 13 12 11 10 9

I

1b

) inputs, allowing the outputs

0

I

Z

0b

b

NOTE:
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual In-Line Package.

SN54/74LS253

DUAL 4-INPUT MULTIPLEXER

WITH 3-STATE OUTPUTS

LOW POWER SCHOTTKY

J SUFFIX

CERAMIC

16

1

16

1

CASE 620-09

N SUFFIX

PLASTIC

CASE 648-08

123456

S1I

E

0a

PIN NAMES LOADING (Note a)

S0, S

1

Multiplexer A

E

0a

I0a–I

3a

Z

a

Multiplexer B

E

0b

I0b–I

3b

Z

b

NOTES:
a) 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.
b) The Output LOW drive factor is 7.5 U.L. for Military (54) and 15 U.L. for Commercial (74)

Temperature Ranges. The Output HIGH drive factor is 25 U.L. for Military (54) and 65 U.L. for
Commercial (74) T emperature Ranges.

3aI2aI1aI0aZa

Common Select Inputs 0.5 U.L. 0.25 U.L.

Output Enable (Active LOW) Input 0.5 U.L. 0.25 U.L.
Multiplexer Inputs 0.5 U.L. 0.25 U.L.
Multiplexer Output (Note b) 65 (25) U.L. 15 (7.5) U.L.

Output Enable (Active LOW) Input 0.5 U.L. 0.25 U.L.
Multiplexer Inputs 0.5 U.L. 0.25 U.L.
Multiplexer Output (Note b) 65 (25) U.L. 15 (7.5) U.L.

7

GND

8

HIGH

LOW

16

1

ORDERING INFORMATION

SN54LSXXXJ Ceramic
SN74LSXXXN Plastic
SN74LSXXXD SOIC

LOGIC SYMBOL

165431011121315

E0aI0aI1aI2aI3aI0bI1bI2bI3bE

14

S

0

2

S

1

Z

a

79

VCC = PIN 16
GND = PIN 8

D SUFFIX

SOIC

CASE 751B-03

Z

b

0b

FAST AND LS TTL DAT A

5-1

LOGIC DIAGRAM

E

0b

SN54/74LS253

I

3b

I

2b

I

1b

I

0b

1113 101215

S

S

0

14 126

I

1

3a

I

345

2a

I

1a

I

E

0a

0a

9

Z

b

VCC = PIN 16
GND = PIN 8

= PIN NUMBERS

FUNCTIONAL DESCRIPTION

The LS253 contains two identical 4-Input Multiplexers with

3-state outputs. They select two bits from four sources
selected by common select inputs (S0, S1). The 4-input
multiplexers have individual Output Enable (E

, E0b) inputs

0a

which when HIGH, forces the outputs to a high impedance
(high Z) state.

The LS253 is the logic implementation of a 2-pole,

4-position switch, where the position of the switch is deter­mined by the logic levels supplied to the two select inputs. The
logic equations for the outputs are shown below:

Za = E

⋅ (I0a ⋅ S1 ⋅ S0 + I1a ⋅ S1 ⋅ S0 ⋅ I2a ⋅ S1 ⋅ S0 + I3a ⋅ S

0a

⋅ S0)
Zb = E

⋅ (I0b ⋅ S1 ⋅ S0 + I1b ⋅ S1 ⋅ S0 ⋅ I2b ⋅ S1 ⋅ S0 + I3b ⋅ S

0b

⋅ S0)

TRUTH TABLE

SELECT

INPUTS

S

S

0

1

X X X X X X H (Z)
L LLXX X L L
L LHXX X L H
H LXLX X L L
HLXHX X L H
L HXXL X L L
LHXXH X L H
HHXXX L L L
HHXXX H L H

H = HIGH Level
L = LOW Level
X = Irrelevant
(Z) = High Impedance (off)
Address inputs S0 and S1 are common to both sections.

I

0

DATA INPUTS

I

1

7

Z

a

If the outputs of 3-state devices are tied together, all but one
device must be in the high impedance state to avoid high
currents that would exceed the maximum ratings. Designers
should ensure that Output Enable signals to 3-state devices
whose outputs are tied together are designed so that there is
no overlap.

1
1

OUTPUT
ENABLE

I

I

2

3

E

0

OUTPUT

Z

FAST AND LS TTL DATA

5-2

SN54/74LS253

VILI

LOW Volt

V

pg

VOHOutput HIGH Volt

CC

,

OH

,

IN IH

VOLOutput LOW Volt

V

V

V

IIHI

HIGH C

t

ICCP

t

GUARANTEED OPERATING RANGES

Symbol Parameter Min Typ Max Unit

V

CC

T

A

I

OH

I

OL

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)

Symbol Parameter

V

IH

V

IK

I

OZH

I

OZL

I

IL

I

OS

Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.

Supply Voltage 54

Operating Ambient Temperature Range 54

Output Current — High 54

Output Current — Low 54

Limits

Min Typ Max

Input HIGH Voltage 2.0 V

nput

Input Clamp Diode Voltage –0.65 –1.5 V VCC = MIN, IIN = –18 mA

Output Off Current HIGH 20 µA VCC = MAX, V
Output Off Current LOW –20 µA VCC = MAX, V

nput

Input LOW Current –0.4 mA VCC = MAX, VIN = 0.4 V
Short Circuit Current (Note 1) –30 –130 mA VCC = MAX

ower Supply Curren

age

age

age

urren

54 0.7
74 0.8

54 2.4 3.4 V
74 2.4 3.1 V

54, 74 0.25 0.4 V IOL = 12 mA

74 0.35 0.5 V IOL = 24 mA

74

74

74

74

20 µA VCC = MAX, VIN = 2.7 V

0.1 mA VCC = MAX, VIN = 7.0 V

12 mA VCC = MAX, VE = 0 V
14

4.5

4.75
–55

0

Unit Test Conditions

Guaranteed Input HIGH Voltage for
All Inputs

Guaranteed Input LOW Voltage for
All Inputs

VCC = MIN, IOH = MAX, VIN = V
or VIL per Truth Table

mA VCC = MAX, VE = 4.5 V

5.0

5.0
25

25

OUT
OUT

5.5

5.25
125

70

–1.0
–2.6

12
24

IH

VCC = VCC MIN,

=

or

IN

IL

per Truth Table

= 2.7 V
= 0.4 V

IH

V

°C

mA

mA

AC CHARACTERISTICS (T

= 25°C, VCC = 5.0 V) See SN54LS251 for Waveforms

A

Symbol Parameter

t

PLH

t

PHL

t

PLH

t

PHL

t

PZH

t

PZL

t

PHZ

t

PLZ

Propagation Delay,
Data to Output

Propagation Delay,
Select to Output

Output Enable Time

Output Disable Time

Limits

Min Typ Max

17
13

30
21

15
15

27
18

25
20

45
32

28
23

41
27

FAST AND LS TTL DATA

5-3

Unit Test Conditions

ns Figure 1

ns Figure 1

ns Figures 4, 5

ns Figures 3, 5

CL = 45 pF,
RL = 667 Ω

CL = 5.0 pF,
RL = 667 Ω