Datasheet SN74ls240 Datasheet

SN54/74LS240 SN54/74LS241

OCTAL BUFFER/LINE DRIVER WITH 3-STATE OUTPUTS

The SN54 /74LS240, 241 and 244 are Octal Buffers and Line Drivers designed to be employed as memory address drivers, clock drivers and bus-oriented transmitters/receivers which provide improved PC board density.

• Hysteresis at Inputs to Improve Noise Margins

• 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers

• Input Clamp Diodes Limit High-Speed Termination Effects

LOGIC AND CONNECTION DIAGRAMS DIP (TOP VIEW)

SN54/74LS240

2G 1Y1 2A4 1Y2 1Y32A3 2A2

V

CC

20 19

1234 56

1G

18 17 16 15 14 13

1A1 2Y4 1A2 2Y3 1A3 2Y2 1A4

SN54/74LS241

2G 1Y1 2A4 1Y2 1Y32A3 2A2

V

CC

20 19

18 17 16 15 14 13

7

1Y4 2A1

8

2Y1 GND

1Y4 2A1

12 11

910

12 11

SN54/74LS244

OCTAL BUFFER/LINE DRIVER

WITH 3-STATE OUTPUTS

LOW POWER SCHOTTKY

J SUFFIX

CERAMIC

20

1

20

1

20

1

CASE 732-03

N SUFFIX

PLASTIC

CASE 738-03

DW SUFFIX

SOIC

CASE 751D-03

1234 56

1A1 2Y4 1A2 2Y3 1A3 2Y2 1A4

1G

SN54/74LS244

2G 1Y1 2A4 1Y2 1Y32A3 2A2

V

CC

20 19

1234 56

1G

18 17 16 15 14 13

1A1 2Y4 1A2 2Y3 1A3 2Y2 1A4

8

2Y1 GND

1Y4 2A1

8

2Y1 GND

910

12 11

910

7

FAST AND LS TTL DAT A

5-1

ORDERING INFORMATION

SN54LSXXXJ Ceramic SN74LSXXXN Plastic SN74LSXXXDW SOIC

SN54/74LS240 • SN54/74LS241 • SN54/74LS244

OUTPUT

TRUTH TABLES

SN54/74LS240

INPUTS

1G, 2G D

L L

H

L H X

H

L

(Z)

SN54/74LS244

INPUTS

1G, 2G D

L L

H

L H X

L

H

(Z)

SN54/74LS241

INPUTS

1G D

L L

H

H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = HIGH Impedance

L H X

L

H

(Z)

INPUTS

2G D

H H

L

L H X

L

H

(Z)

GUARANTEED OPERATING RANGES

Symbol Parameter Min Typ Max Unit

V

T

I

CC

A

OH

OL

Supply Voltage 54

Operating Ambient Temperature Range 54

Output Current — High

Output Current — Low 54

74

54, 74 –3.0 mA

54 74

74

4.5

4.75 –55

0

5.0

5.0 25

25

5.5

5.25 125

70

–12 –15

12 24

V

°C

mA

FAST AND LS TTL DATA

5-2

SN54/74LS240 • SN54/74LS241 • SN54/74LS244

VILI

LOW Volt

V

pg

VOHOutput HIGH Volt

VOLOutput LOW Volt

V

IIHI

HIGH C

t

L

p,

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)

Limits

Symbol Parameter

V

IH

VT+–V

T–

V

IK

I

OZH

I

OZL

I

IL

I

OS

I

CC

Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.

Input HIGH Voltage 2.0 V

nput

Hysteresis 0.2 0.4 V VCC = MIN Input Clamp Diode Voltage –0.65 –1.5 V VCC = MIN, IIN = –18 mA

Output Off Current HIGH 20 µA VCC = MAX, V Output Off Current LOW –20 µA VCC = MAX, V

nput

Input LOW Current –0.2 mA VCC = MAX, VIN = 0.4 V Output Short Circuit Current (Note 1) –40 –225 mA VCC = MAX Power Supply Current

Total, Output HIGH Total, Output LOW LS240 44

Total at HIGH Z LS240 50

age

urren

54 0.7 74 0.8

54, 74 2.4 3.4 V VCC = MIN, IOH = –3.0 mA 54, 74 2.0 V VCC = MIN, IOH = MAX

54, 74 0.25 0.4 V IOL = 12 mA

74 0.35 0.5 V IOL = 24 mA

LS241/244 46

LS241/244 54

Min Typ Max

20 µA VCC = MAX, VIN = 2.7 V

0.1 mA VCC = MAX, VIN = 7.0 V

27

Unit Test Conditions

Guaranteed Input HIGH Voltage for All Inputs

Guaranteed Input LOW Voltage for All Inputs

mA VCC = MAX

VCC = VCC MIN,

=

IN

per Truth Table

= 2.7 V

OUT

= 0.4 V

OUT

or

IL

IH

AC CHARACTERISTICS (T

Symbol Parameter

t

PLH

t

PHL

t

PLH

t

PHL

t

PZH

t

PZL

t

PLZ

t

PHZ

Propagation Delay, Data to Output LS240

Propagation Delay, Data to Output LS241/244

Output Enable Time to HIGH Level 15 23 ns Output Enable Time to LOW Level 20 30 ns Output Disable Time from LOW Level 15 25 ns Output Disable Time from HIGH Level 10 18 ns

A

= 25°C, VCC = 5.0 V)

Limits

Min Typ Max

9.0 12

12 12

14 18

18 18

FAST AND LS TTL DATA

5-3

Unit Test Conditions

ns

CL = 45 pF, RL = 667 Ω

CL = 5.0 pF,

RL = 667 Ω

SN54/74LS240 • SN54/74LS241 • SN54/74LS244

AC WAVEFORMS

V

1.3 V 1.3 V

IN

V

OUT

t

PLH

1.3 V

t

PHL

1.3 V

V

CC

R

L

V V

E E

V

OUT

Figure 1

IN

OUT

1.3 V t

PHL

1.3 V

V

Figure 2

1.3 V 1.3 V t

PZL

1.3 V

Figure 3

1.3 V

0.5 V

t

PLH

1.3 V

t

PLZ

V

≈

1.3 V

OL

TO OUTPUT

UNDER TEST

SYMBOL SW1 SW2

t

PZH

t

PZL

t

PLZ

t

PHZ

SW1

Ω

5 k

SW2CL*

SWITCH POSITIONS

Open Closed Closed Open Closed Closed Closed Closed

Figure 5

V

E

V

E

V

1.3 V 1.3 V t

PZH

OUT

1.3 V

t

PHZ

≥

≈

0.5 V

V

OH

1.3 V

Figure 4

FAST AND LS TTL DATA

5-4