Datasheet SN74ls173 Datasheet

4-BIT D-TYPE REGISTER WITH 3-STATE OUTPUTS

The SN54/74LS173A is a high-speed 4-Bit Register featuring 3-state outputs for use in bus-organized systems. The clock is fully edge-triggered allowing either a load from the D inputs or a hold (retain register contents) depending on the state of the Input Enable Lines (IE1, IE2). A HIGH on either Output Enable line (OE without affecting the actual register contents. A HIGH on the Master Reset (MR) input resets the Register regardless of the state of the Clock (CP), the Output Enable (OE

• Fully Edge-Triggered

• 3-State Outputs

• Gated Input and Output Enables

• Input Clamp Diodes Limit High-Speed Termination Effects

, OE2) brings the output to a high impedance state

1

, OE2) or the Input Enable (IE1, IE2) lines.

1

SN54/74LS173A

4-BIT D-TYPE REGISTER WITH 3-STATE OUTPUTS

LOW POWER SCHOTTKY

J SUFFIX

CERAMIC

16

1

CASE 620-09

CONNECTION DIAGRAM DIP (TOP VIEW)

MR D0D1D

V

CC

16 15

123456

OE

1

PIN NAMES LOADING (Note a)

D0–D

3

IE

–IE

1

2

OE

–OE

1

CP

MR Q0–Q

3

NOTES: a. 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW. b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)

b. T emperature Ranges.

14 13 12 11 10 9

OE

2Q0Q1Q2Q3

Data Inputs Input Enable (Active LOW) Output Enable (Active LOW) Inputs

2

Clock Pulse (Active HIGH Going Edge) Input Master Reset Input (Active HIGH) Outputs (Note b)

2

D

3

IE

2

8

7

CP GND

1

NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package.

HIGH

0.5 U.L.

65 (25) U.L.

LOW

15 (7.5) U.L.

0.25 U.L.

16

1

16

1

CASE 648-08

CASE 751B-03

ORDERING INFORMATION

SN54LSXXXJ Ceramic SN74LSXXXN Plastic SN74LSXXXD SOIC

LOGIC SYMBOL

910 14131211

1 2

7 1

1 2

2

IE

CP OE

D0D1D2D

MR

N SUFFIX

PLASTIC

D SUFFIX

SOIC

3

Q1Q0Q2Q

3

FAST AND LS TTL DAT A

5-1

345615

VCC = PIN 16 GND = PIN 8

LOGIC DIAGRAM

SN54/74LS173A

IE

9

1

10

IE

2

CP

7

15

MR

1

OE

1

OE

2

VCC = PIN 16 GND = PIN 8

= PIN NUMBERS

D

0

14

C

P

D

1

13

D D D

QDQ

3 4 5

Q

0

Q

1

D

2

Q

2

D

3

1112

6

Q

3

TRUTH TABLE

MR CP IE

1

H x x x x L L L x x x Q L H x x Q L x H x Q L L L L L L L L H H

When either OE however this does not affect the contents or sequential operation of the register.

, or OE2 are HIGH, the output is in the off state (High Impedance);

1

IE

2

D

n

Q

n

n n n

H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial

GUARANTEED OPERATING RANGES

Symbol Parameter Min Typ Max Unit

V

T

I

OH

I

OL

CC

A

Supply Voltage 54

74

Operating Ambient Temperature Range 54

74

Output Current — High 54

74

Output Current — Low 54

74

4.5

4.75 –55

0

5.0

5.0 25

25

5.5

5.25 125

70

–1.0 –2.6

12 24

V

°C

mA

FAST AND LS TTL DATA

5-2

SN54/74LS173A

VILI

LOW Volt

V

pg

VOHOutput HIGH Volt

CC

,

OH

,

IN IH

VOLOutput LOW Volt

V

IIHI

HIGH C

t

C

L

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)

Limits

Symbol Parameter

V

IH

V

IK

I

OZH

I

OZL

I

IL

I

OS

I

CC

Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.

Input HIGH Voltage 2.0 V

nput

Input Clamp Diode Voltage –0.65 –1.5 V VCC = MIN, IIN = –18 mA

Output Off Current HIGH 20 µA VCC = MAX, VO = 2.7 V Output Off Current LOW –20 µA VCC = MAX, VO = 0.4 V

nput

Input LOW Current –0.4 mA VCC = MAX, VIN = 0.4 V Short Circuit Current (Note 1) –30 –130 mA VCC = MAX Power Supply Current 30 mA VCC = MAX

age

urren

54 0.7 74 0.8

54 2.4 3.4 V 74 2.4 3.1 V

54, 74 0.25 0.4 V IOL = 12 mA

74 0.35 0.5 V IOL = 24 mA

Min Typ Max

20 µA VCC = MAX, VIN = 2.7 V

0.1 mA VCC = MAX, VIN = 7.0 V

Unit Test Conditions

Guaranteed Input HIGH Voltage for All Inputs

Guaranteed Input LOW Voltage for All Inputs

VCC = MIN, IOH = MAX, VIN = V or VIL per Truth Table

IH

VCC = VCC MIN,

=

or

IN

IL

per Truth Table

IH

AC CHARACTERISTICS (T

Symbol Parameter

f

MAX

t

PLH

t

PHL

t

PHL

t

PZH

t

PZL

t

PLZ

t

PHZ

Maximum Input Clock Frequency 30 50 MHz Propagation Delay,

Clock to Output Propagation Delay, MR to Output 26 35 ns

Output Enable Time

Output Disable Time

= 25°C)

A

AC SETUP REQUIREMENTS (T

Symbol Parameter

t t t t t

W s s h rec

Clock or MR Pulse Width 20 ns Data Enable Setup Time 35 ns Data Setup Time 17 ns Hold Time, Any Input 0 ns Recovery Time 10 ns

= 25°C)

A

Limits

Min Typ Max

17 22

15 18

11 11

Limits

Min Typ Max

25 30

23 27

17 17

Unit Test Conditions

ns

Unit Test Conditions

VCC = 5.0 V

= 45 pF,

L

RL = 667 Ω

CL = 5.0 pF,

RL = 667 Ω

VCC = 5.0 V

FAST AND LS TTL DATA

5-3

SN54/74LS173A

AC WAVEFORMS

CP

D or E

Q

V

E

OUT

t

s(H)

1.3 V

t

PLH

1 / fmax

t

h(H)

1.3 V

t

s(L)

t

W

Figure 1 Figure 2

1.3 V 1.3 V t

PLZ

Figure 3 Figure 4

t

PHL

1.3 V

0.5 V

t

h(L)

1.3 V

t

PZL

1.3 V V

OL

MR

CP

V

Q

E

OUT

t

W

1.3 V

1.3 V 1.3 V t

PZH

1.3 V

t

PHL

t

1.3 V

t

PHZ

rec

≥

V

0.5 V

OH

≈

1.3 V

TO OUTPUT

UNDER TEST

AC LOAD CIRCUIT

V

CC

R

L

SW1

Ω

5 k

CL*

*Includes Jig and Probe Capacitance.

SW2

Figure 5

SWITCH POSITIONS

SYMBOL SW1 SW2

t

PZH

t

PZL

t

PLZ

t

PHZ

Open Closed Closed Open Closed Closed Closed Closed

FAST AND LS TTL DATA

5-4