Datasheet SN74LS166D, SN74LS166M, SN74LS166MEL, SN74LS166ML1, SN74LS166MR1 Datasheet (MOTOROLA)

 Semiconductor Components Industries, LLC, 1999

December, 1999 – Rev. 6

1 Publication Order Number:

SN74LS166/D

SN74LS166

8-Bit Shift Registers

The SN74LS166 is an 8-Bit Shift Register. Designed with all inputs
buffered, the drive requirements are lowered to one 74LS standard
load. By utilizing input clamping diodes, switching transients are
minimized and system design simplified.

The LS166 is a parallel-in or serial-in, serial-out shift register and
has a complexity of 77 equivalent gates with gated clock inputs and an
overriding clear input. The shift/load input establishes the parallel-in
or serial-in mode. When high, this input enables the serial data input
and couples the eight flip-flops for serial shifting with each clock
pulse. Synchronous loading occurs on the next clock pulse when this is
low and the parallel data inputs are enabled. Serial data flow is
inhibited during parallel loading. Clocking is done on the low-to-high
level edge of the clock pulse via a two input positive NOR gate, which
permits one input to be used as a clock enable or clock inhibit function.
Clocking is inhibited when either of the clock inputs are held high,
holding either input low enables the other clock input. This will allow
the system clock to be free running and the register stopped on
command with the other clock input. A change from low-to-high on
the clock inhibit input should only be done when the clock input is
high. A buffered direct clear input overrides all other inputs, including
the clock, and sets all flip-flops to zero.

• Synchronous Load

• Direct Overriding Clear

• Parallel to Serial Conversion

GUARANTEED OPERATING RANGES

Symbol Parameter Min Typ Max Unit

V

CC

Supply Voltage 4.75 5.0 5.25 V

T

A

Operating Ambient

T emperature Range

0 25 70 °C

I

OH

Output Current – High –0.4 mA

I

OL

Output Current – Low 8.0 mA

LOW

POWER

SCHOTTKY

Device Package Shipping

ORDERING INFORMATION

SN74LS166N 16 Pin DIP 2000 Units/Box
SN74LS166D 16 Pin

SOIC

D SUFFIX

CASE 751B

http://onsemi.com

2500/Tape & Reel

PLASTIC
N SUFFIX
CASE 648

16

1

16

1

SN74LS166

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2

14 13 12 11 10 9

123456

7

16 15

8

V

CC

SERIAL

INPUT

SHIFT/

LOAD

HQ

H

GEF CLEAR

A B C D CLOCK

INHIBIT

CLOCK GND

PARALLEL PARALLEL INPUTS

INPUT OUTPUT

PARALLEL INPUTS

SHIFT/

LOAD
SERIAL INPUT

CLOCK
INHIBIT

HQHGFE

ABC D

CK

CLEAR

FUNCTION TABLE

INPUTS

INTERNAL

SHIFT/ CLOCK

PARALLEL

OUTPUTS

OUTPUT

Q

CLEAR

LOAD INHIBIT

CLOCK

SERIAL

A . . . H Q

A

Q

B

Q

H

L X X X X X L L L
H X L L X X Q

A0

Q

B0

Q

H0

H L L ↑ X a . . . h a b h
H H L ↑ H X H Q

An

Q

Gn

H H L ↑ L X L Q

An

Q

Gn

H X H ↑ X X Q

A0

Q

B0

Q

H0

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3

Typical Clear, Shift, Load, Inhibit, and Shift Sequences

PARALLEL

INPUTS

A
B

C
D

CLOCK INIHIBIT

CLOCK

SHIFT/LOAD

H

OUTPUT Q

H

G

F

E

CLEAR

SERIAL INPUT

H

H

H

H
H

L

L

L

HH H H H

LL

L

CLEAR

SERIAL SHIFT

LOAD

INHIBIT

SERIAL SHIFT

CLEAR

SERIAL INPUT

SHIFT/LOAD

A

B

C

D

H

G

F

E

(9)
(1)

(15)
(2)

(3)

(4)

(5)

(10)

(11)

(12)

(14)
(7)

(6)

CLOCK INHIBIT

CLOCK

(13)

RCKS

Q

A

RCKS

Q

B

RCKS

Q

C

RCKS

Q

D

RCKS

Q

E

RCKS

Q

F

RCKS

Q

G

RCKS

Q

H

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4

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)

Limits

Symbol Parameter

Min Typ Max

Unit Test Conditions

V

IH

Input HIGH Voltage 2.0 V

Guaranteed Input HIGH Voltage for
All Inputs

V

IL

Input LOW Voltage

0.8
V

Guaranteed Input LOW Voltage for
All Inputs

V

IK

Input Clamp Diode Voltage –0.65 –1.5 V VCC = MIN, IIN = –18 mA

V

OH

Output HIGH Voltage 2.7 3.5 V VCC = MIN, IOH = MAX, VIN = V

IH

or VIL per Truth Table

p

0.25 0.4 V IOL = 4.0 mA

VCC = VCC MIN,

VOLOutput LOW Voltage

0.35 0.5 V IOL = 8.0 mA

V

IN

=

V

IL

or

V

IH

per Truth Table

p

20 µA VCC = MAX, VIN = 2.7 V

IIHInput HIGH Current

0.1 mA VCC = MAX, VIN = 7.0 V

I

IL

Input LOW Current –0.4 mA VCC = MAX, VIN = 0.4 V

I

OS

Short Circuit Current (Note 1) –20 –100 mA VCC = MAX

I

CC

Power Supply Current 38 mA VCC = MAX

Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.

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5

TEST TABLE FOR SYNCHRONOUS INPUTS

DATA INPUT

FOR TEST

SHIFT/LOAD OUTPUT TESTED

H 0 V QH at t

n+1

Serial

Input

4.5 V QH at t

n+8

AC WAVEFORMS

NOTE 1. tn = bit time before clocking transition

NOTE 1. t

n+1

= bit time after one clocking transition

NOTE 1. t

n+8

= bit time after eight clocking transition

NOTE 1. LS166 V

ref

= 1.3 V.

CLEAR INPUT

CLOCK INPUT

DATA
INPUT
(SEE TEST
TABLE)

OUTPUT Q

V

ref

t

w(clear)

t

PHL

(clear-Q)

(SEE NOTE 1)

t

n + 1

t

n

t

su

t

h

t

PLH

(CLK-Q)

3 V

0 V

V

OH

V

OL

3 V

3 V

0 V

0 V

V

ref

V

ref

V

ref

V

ref

V

ref

V

ref

V

ref

V

ref

t

n

t

n + 1

t

su

t

h

t

PHL

t

w(clock)

(CLK-Q)

V

ref

V

ref

V

ref

AC CHARACTERISTICS (T

A

= 25°C)

Limits

Symbol Parameter

Min Typ Max

Unit Test Conditions

f

MAX

Maximum Clock Frequency 25 35 MHz

t

PHL

Clear to Output 19 30 ns

VCC = 5.0 V

t

PLH

t

PHL

Clock to Output

23
24

35
35

ns

CL = 15 pF

AC SETUP REQUIREMENTS (T

A

= 25°C)

Limits

Symbol Parameter

Min Typ Max

Unit Test Conditions

t

W

Clock Clear Pulse Width 30 ns

t

s

Mode Control Setup Time 30 ns

t

s

Data Setup Time 20 ns

V

CC

= 5.0

V

t

h

Hold Time, Any Input 15 ns

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6

P ACKAGE DIMENSIONS

N SUFFIX

PLASTIC PACKAGE

CASE 648–08

ISSUE R

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

–A–

B

F

C

S

H

G

D

J

L

M

16 PL

SEATING

18

916

K

PLANE

–T–

M

A

M

0.25 (0.010) T

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A 0.740 0.770 18.80 19.55
B 0.250 0.270 6.35 6.85
C 0.145 0.175 3.69 4.44
D 0.015 0.021 0.39 0.53
F 0.040 0.70 1.02 1.77
G 0.100 BSC 2.54 BSC
H 0.050 BSC 1.27 BSC
J 0.008 0.015 0.21 0.38
K 0.110 0.130 2.80 3.30
L 0.295 0.305 7.50 7.74
M 0 10 0 10
S 0.020 0.040 0.51 1.01

____

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7

P ACKAGE DIMENSIONS

D SUFFIX

PLASTIC SOIC PACKAGE

CASE 751B–05

ISSUE J

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.

18

16 9

SEATING

PLANE

F

J

M

R

X 45

_

G

8 PLP

–B–

–A–

M

0.25 (0.010) B

S

–T–

D

K

C

16 PL

S

B

M

0.25 (0.010) A

S

T

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A 9.80 10.00 0.386 0.393
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019

F 0.40 1.25 0.016 0.049

G 1.27 BSC 0.050 BSC

J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009
M 0 7 0 7

P 5.80 6.20 0.229 0.244
R 0.25 0.50 0.010 0.019

____

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8

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