Datasheet SN74LS165D, SN74LS165DR2, SN74LS165MEL, SN74LS165MR1, SN74LS165N Datasheet (MOTOROLA)
Page 1
Semiconductor Components Industries, LLC, 1999
December, 1999 – Rev. 6
1 Publication Order Number:
SN74LS165/D
SN74LS165
8-Bit Parallel-to-Serial
Shift Register
The SN74LS165 is an 8-bit parallel load or serial-in register with
complementary outputs available from the last stage. Parallel inputing
occurs asynchronously when the Parallel Load (PL
) input is LOW.
With PL HIGH, serial shifting occurs on the rising edge of the clock;
new data enters via the Serial Data (DS) input. The 2-input OR clock
can be used to combine two independent clock sources, or one input
can act as an active LOW clock enable.
GUARANTEED OPERATING RANGES
Symbol Parameter Min Typ Max Unit
V
CC
Supply Voltage 4.75 5.0 5.25 V
T
A
Operating Ambient
T emperature Range
0 25 70 °C
I
OH
Output Current – High –0.4 mA
I
OL
Output Current – Low 8.0 mA
LOW
POWER
SCHOTTKY
Device Package Shipping
ORDERING INFORMATION
SN74LS165N 16 Pin DIP 2000 Units/Box
SN74LS165D 16 Pin
SOIC
D SUFFIX
CASE 751B
http://onsemi.com
2500/Tape & Reel
PLASTIC
N SUFFIX
CASE 648
16
1
16
1
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2
CONNECTION DIAGRAM DIP (TOP VIEW)
Clock (LOW–to–HIGH Going Edge) Inputs
Serial Data Input
Asynchronous Parallel Load (Active LOW) Input
Parallel Data Inputs
Serial Output from Last State
Complementary Output
CP
1
, CP
2
DS
PL
P0 – P
7
Q
7
Q
7
0.5 U.L.
0.5 U.L.
1.5 U.L.
0.5 U.L.
10 U.L.
10 U.L.
0.25 U.L.
0.25 U.L.
0.75 U.L.
0.25 U.L.
5 U.L.
5 U.L.
NOTES:
a) 1 TTL Unit Load (U.L.) = 40 mA HIGH/1.6 mA LOW.
HIGH LOW
(Note a)LOADING
PIN NAMES
VCC = PIN 16
GND = PIN 8
LOGIC SYMBOL
NOTE:
The Flatpak version has the same
pinouts (Connection Diagram) as
the Dual In-Line Package.
11112131434 56
9
7
10
2
15
D
S
CP
Q
7
Q
7
PL P0P1P2P3P4P5P6P
7
14 13 12 11 10 9
123456
7
16 15
8
V
CC
PL
CP2P3P2P
1
DSP
0
Q
7
CP1P4P5P6P7Q7GND
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LOGIC DIAGRAM
PL
CP
1
P
4
P
6
P
5
P
7
CP
2
P
3
P
1
P
2
P
0
D
S
PRESET
S
CP
R
C
L
Q
0
Q
0
PRESET
S
CP
R
C
L
Q
1
Q
1
PRESET
S
CP
R
C
L
Q
2
Q
2
PRESET
S
CP
R
C
L
Q
3
Q
3
PRESET
S
CP
R
C
L
Q
4
Q
4
PRESET
S
CP
R
C
L
Q
5
Q
5
PRESET
S
CP
R
C
L
Q
6
Q
6
PRESET
S
CP
R
C
L
Q
7
Q
7
14
1
2
6
3 4 511 12
10
13
15
VCC = PIN 16
GND = PIN 8
= PIN NUMBERS
7
9
FUNCTIONAL DESCRIPTION
The SN74LS165 contains eight clocked master/slave RS
flip-flops connected as a shift register, with auxiliary gating
to provide overriding asynchronous parallel entry. Parallel
data enters when the PL
signal is LOW . The parallel data can
change while PL is LOW, provided that the recommended
setup and hold times are observed.
For clock operation, PL must be HIGH. The two clock
inputs perform identically; one can be used as a clock inhibit
by applying a HIGH signal. To avoid double clocking,
however, the inhibit signal should only go HIGH while the
clock is HIGH. Otherwise, the rising inhibit signal will cause
the same response as a rising clock edge. The flip-flops are
edge-triggered for serial operations. The serial input data
can change at any time, provided only that the recommended
setup and hold times are observed, with respect to the rising
edge of the clock.
TRUTH TABLE
CP CONTENTS
PL
1 2 Q0Q1Q2Q3Q4Q5Q6Q
7
RESPONSE
L X X P0P1P2P3P4P5P6P7Parallel Entry
H L DSQ0Q1Q2Q3Q4Q5Q
6
Right Shift
H H Q0Q1Q2Q3Q4Q5Q6Q
7
No Change
H L DSQ0Q1Q2Q3Q4Q5Q
6
Right Shift
H H Q0Q1Q2Q3Q4Q5Q6Q
7
No Change
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
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DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits
Symbol Parameter
Min Typ Max
Unit Test Conditions
V
IH
Input HIGH Voltage 2.0 V
Guaranteed Input HIGH Voltage for
All Inputs
V
IL
Input LOW Voltage
0.8
V
Guaranteed Input LOW Voltage for
All Inputs
V
IK
Input Clamp Diode Voltage –0.65 –1.5 V VCC = MIN, IIN = –18 mA
V
OH
Output HIGH Voltage 2.7 3.5 V VCC = MIN, IOH = MAX, VIN = V
IH
or VIL per Truth Table
p
0.25 0.4 V IOL = 4.0 mA
VCC = VCC MIN,
VOLOutput LOW Voltage
0.35 0.5 V IOL = 8.0 mA
V
IN
=
V
IL
or
V
IH
per Truth Table
I
IH
Input HIGH Current
Other Inputs
PL
Input
20
60
µA VCC = MAX, VIN = 2.7 V
IH
Other Inputs
PL
Input
0.1
0.3
mA VCC = MAX, VIN = 7.0 V
I
IL
Input LOW Current
Other Inputs
PL
Input
–0.4
–1.2
mA VCC = MAX, VIN = 0.4 V
I
OS
Short Circuit Current (Note 1) –20 –100 mA VCC = MAX
I
CC
Power Supply Current 36 mA VCC = MAX
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS (T
A
= 25°C)
Limits
Symbol Parameter
Min Typ Max
Unit Test Conditions
f
MAX
Maximum Input Clock Frequency 25 35 MHz
t
PLH
t
PHL
Propagation Delay
PL
to Output
22
22
35
35
ns
t
PLH
t
PHL
Propagation Delay
Clock to Output
27
28
40
40
ns
VCC = 5.0 V
C
= 15 pF
t
PLH
t
PHL
Propagation Delay
P
7
to Q
7
14
21
25
30
ns
C
L
15
F
t
PLH
t
PHL
Propagation Delay
P
7
to Q
7
21
16
30
25
ns
AC SETUP REQUIREMENTS (T
A
= 25°C)
Limits
Symbol Parameter
Min Typ Max
Unit Test Conditions
t
W
CP Clock Pulse Width 25 ns
t
W
PL Pulse Width 15 ns
t
s
Parallel Data Setup Time 10 ns
t
s
Serial Data Setup Time 20 ns
VCC = 5.0 V
t
s
CP1 to CP2 Setup Time
1
30 ns
t
h
Hold Time 0 ns
t
rec
Recovery Time, PL to CP 45 ns
1
The role of CP1 and CP2 in an application may be interchanged.
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DEFINITION OF TERMS:
SETUP TIME (ts) — is defined as the minimum time
required for the correct logic level to be present at the logic
input prior to the clock transition from LOW-to-HIGH in
order to be recognized and transferred to the outputs.
HOLD TIME (t
h
) — is defined as the minimum time
following the clock transition from LOW-to-HIGH that the
logic level must be maintained at the input in order to ensure
continued recognition. A negative hold time indicates that
the correct logic level may be released prior to the clock
transition from LOW-to-HIGH and still be recognized.
RECOVER Y TIME (t
rec
) — is defined as the minimum time
required between the end of the PL pulse and the clock
transition from LOW-to-HIGH in order to recognize and
transfer loaded Data to the Q outputs.
AC WAVEFORMS
t
W
1.3 V 1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V 1.3 V
1.3 V 1.3 V
1.3 V
CP
1
CP
2
Q7 OR Q
7
P
n
PL OR CP
t
PHL
t
PLH
PL
CP
t
rec
Q7 OR Q
7
PL
t
PHL
t
PLH
t
W
t
W
1/f
max
t
s
t
s(H)
t
h(H)
t
s(L)
t
h(L)
Figure 1. Figure 2.
1.3 V
Figure 3. Figure 4.
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P ACKAGE DIMENSIONS
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
ISSUE R
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
–A–
B
F
C
S
H
G
D
J
L
M
16 PL
SEATING
18
916
K
PLANE
–T–
M
A
M
0.25 (0.010) T
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A 0.740 0.770 18.80 19.55
B 0.250 0.270 6.35 6.85
C 0.145 0.175 3.69 4.44
D 0.015 0.021 0.39 0.53
F 0.040 0.70 1.02 1.77
G 0.100 BSC 2.54 BSC
H 0.050 BSC 1.27 BSC
J 0.008 0.015 0.21 0.38
K 0.110 0.130 2.80 3.30
L 0.295 0.305 7.50 7.74
M 0 10 0 10
S 0.020 0.040 0.51 1.01
____
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P ACKAGE DIMENSIONS
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
18
16 9
SEATING
PLANE
F
J
M
R
X 45
_
G
8 PLP
–B–
–A–
M
0.25 (0.010) B
S
–T–
D
K
C
16 PL
S
B
M
0.25 (0.010) A
S
T
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A 9.80 10.00 0.386 0.393
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
F 0.40 1.25 0.016 0.049
G 1.27 BSC 0.050 BSC
J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009
M 0 7 0 7
P 5.80 6.20 0.229 0.244
R 0.25 0.50 0.010 0.019
____
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