Datasheet SN74ls165 Datasheet

8-BIT PARALLEL-TO-SERIAL

PL

RESPONSE

SHIFT REGISTER

The SN54/74LS165 is an 8-bit parallel load or serial-in register with complementary outputs available from the last stage. Parallel inputing occurs asynchronously when the Parallel Load (PL serial shifting occurs on the rising edge of the clock; new data enters via the Serial Data (DS) input. The 2-input OR clock can be used to combine two independent clock sources, or one input can act as an active LOW clock enable.

CONNECTION DIAGRAM DIP (TOP VIEW)

V

CP2P3P2P

CC

16 15

14 13 12 11 10 9

1

0

) input is LOW. With PL HIGH,

DSP

Q

7

NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package.

SN54/74LS165

8-BIT PARALLEL-TO-SERIAL

SHIFT REGISTER

LOW POWER SCHOTTKY

J SUFFIX

CERAMIC

16

1

CASE 620-09

123456

PL

CP1P4P5P6P7Q

PIN NAMES LOADING (Note a)

CP1, CP DS PL

P0–P Q

7

Q

7

NOTES: a) 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW. b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)

T emperature Ranges.

Clock (LOW-to-HIGH Going Edge) Inputs

2

Serial Data Input Asynchronous Parallel Load (Active LOW)

Input

Parallel Data Inputs

7

Serial Output from Last State (Note b) Complementary Output (Note b)

7

GND

7

8

HIGH

0.5 U.L.

1.5 U.L.

0.5 U.L. 10 U.L. 10 U.L.

LOW

0.25 U.L.

0.75 U.L.

0.25 U.L. 5 (2.5) U.L. 5 (2.5) U.L.

TRUTH TABLE

CP CONTENTS

1 2 Q0Q1Q2Q3Q4Q5Q6Q

L X X P0P1P2P3P4P5P6P7Parallel Entry H L DSQ0Q1Q2Q3Q4Q5Q H H Q0Q1Q2Q3Q4Q5Q6Q H L DSQ0Q1Q2Q3Q4Q5Q H H Q0Q1Q2Q3Q4Q5Q6Q

H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial

7

6 7 6 7

Right Shift

No Change

Right Shift

No Change

16

1

16

1

ORDERING INFORMATION

SN54LSXXXJ Ceramic SN74LSXXXN Plastic SN74LSXXXD SOIC

LOGIC SYMBOL

111121314 34 5 6

10

2

15

PL P0P1P2P3P4P5P6P

D

S

CP

N SUFFIX

PLASTIC

CASE 648-08

D SUFFIX

SOIC

CASE 751B-03

7

Q

7

Q

7

9 7

VCC = PIN 16 GND = PIN 8

FAST AND LS TTL DAT A

5-1

SN54/74LS165

LOGIC DIAGRAM

10

D

S

CP

2

1

15

CP

2

PL

1

P

0

PRESET

Q

S

0

CP

Q

R

C

0

L

P

1

PRESET

Q

S

1

CP

Q

R

C

1

L

13

PRESET S CP

R

C

VCC = PIN 16 GND = PIN 8

= PIN NUMBERS

FUNCTIONAL DESCRIPTION

The SN54/74LS165 contains eight clocked master/slave RS flip-flops connected as a shift register, with auxiliary gating to provide overriding asynchronous parallel entry. Parallel data enters when the PL change while PL

is LOW, provided that the recommended set-

signal is LOW. The parallel data can

up and hold times are observed.

For clock operation, PL

must be HIGH. The two clock inputs

perform identically; one can be used as a clock inhibit by

14

P

2

Q

2

Q

2

L

P

3

PRESET

Q

S

3

CP

Q

R

C

3

L

P

4

PRESET

Q

S

4

CP

Q

R

C

4

L

P

5

PRESET

Q

S

5

CP

Q

R

C

5

L

P

6

PRESET

Q

S

6

CP

Q

R

C

6

L

63 4 511 12

P

7

PRESET

Q

S

7

CP

Q

R

C

7

L

9

7

applying a HIGH signal. To avoid double clocking, however, the inhibit signal should only go HIGH while the clock is HIGH. Otherwise, the rising inhibit signal will cause the same response as a rising clock edge. The flip-flops are edge-triggered for serial operations. The serial input data can change at any time, provided only that the recommended setup and hold times are observed, with respect to the rising edge of the clock.

GUARANTEED OPERATING RANGES

Symbol Parameter Min Typ Max Unit

V

T

I

OH

I

OL

CC

A

Supply Voltage 54

74

Operating Ambient Temperature Range 54

74

4.5

4.75 –55

0

5.0

5.0 25

25

5.5

5.25 125

70 Output Current — High 54, 74 –0.4 mA Output Current — Low 54

74

4.0

8.0

V

°C

mA

FAST AND LS TTL DATA

5-2

SN54/74LS165

VILI

LOW Volt

V

pg

VOHOutput HIGH Volt

CC

,

OH

,

IN IH

VOLOutput LOW Volt

V

I

IH

C

L

pF

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)

Limits

Symbol Parameter

V

IH

V

IK

I

IH

I

IL

I

OS

I

CC

Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.

Input HIGH Voltage 2.0 V

nput

Input Clamp Diode Voltage –0.65 –1.5 V VCC = MIN, IIN = –18 mA

Input HIGH Current

Other Inputs PL

Input

Other Inputs PL

Input

Input LOW Current

Other Inputs PL

Input Short Circuit Current (Note 1) –20 –100 mA VCC = MAX Power Supply Current 36 mA VCC = MAX

age

54 0.7 74 0.8

54 2.5 3.5 V 74 2.7 3.5 V

54, 74 0.25 0.4 V IOL = 4.0 mA

74 0.35 0.5 V IOL = 8.0 mA

Min Typ Max

20 60

0.1

0.3

–0.4 –1.2

Unit Test Conditions

Guaranteed Input HIGH Voltage for All Inputs

Guaranteed Input LOW Voltage for All Inputs

VCC = MIN, IOH = MAX, VIN = V or VIL per Truth Table

µA VCC = MAX, VIN = 2.7 V

mA VCC = MAX, VIN = 7.0 V

mA VCC = MAX, VIN = 0.4 V

IH

VCC = VCC MIN,

=

or

IN

IL

per Truth Table

IH

AC CHARACTERISTICS (T

Symbol Parameter

f

MAX

t

PLH

t

PHL

t

PLH

t

PHL

t

PLH

t

PHL

t

PLH

t

PHL

Maximum Input Clock Frequency 25 35 MHz Propagation Delay

PL

to Output

Propagation Delay Clock to Output

Propagation Delay P7 to Q

A

7

= 25°C)

Limits

Min Typ Max

22 22

27 28

14 21

21 16

35 35

40 40

25 30

30 25

Unit Test Conditions

ns

VCC = 5.0 V

C

= 15 pF

= 15

FAST AND LS TTL DATA

5-3

SN54/74LS165

AC SETUP REQUIREMENTS (T

Symbol Parameter

t

W

t

W

t

s

t

s

t

s

t

h

t

rec

1

The role of CP1, and CP2 in an application may be interchanged.

CP Clock Pulse Width 25 ns PL Pulse Width 15 ns Parallel Data Setup Time 10 ns Serial Data Setup Time 20 ns CP1 to CP2 Setup Time Hold Time 0 ns Recovery Time, PL to CP 45 ns

= 25°C)

A

Min Typ Max

1

30 ns

DEFINITION OF TERMS:

SETUP TIME (ts) — is defined as the minimum time required for the correct logic level to be present at the logic input prior to the clock transition from LOW-to-HIGH in order to be recognized and transferred to the outputs.

HOLD TIME (th) — is defined as the minimum time following the clock transition from LOW-to-HIGH that the logic level must be maintained at the input in order to ensure continued

Limits

Unit Test Conditions

VCC = 5.0 V

recognition. A negative hold time indicates that the correct logic level may be released prior to the clock transition from LOW-to-HIGH and still be recognized.

RECOVERY TIME (t required between the end of the PL

) — is defined as the minimum time

rec

pulse and the clock transition from LOW-to-HIGH in order to recognize and transfer loaded Data to the Q outputs.

CP

Q7 OR Q

PL OR CP

1

t

PHL

1.3 V

1/f

max

t

s

1.3 V 1.3 V

2

7

Figure 1

t

s(H)

1.3 V

t

h(H)

P

n

Figure 3

t

s(L)

AC WAVEFORMS

t

W

PL

7

1.3 V

t

PLH

t

W

t

PLH

1.3 V

Q7 OR Q

1.3 V 1.3 V t

PHL

1.3 V 1.3 V

Figure 2

1.3 V

t

h(L)

PL

CP

1.3 V t

W

1.3 V

t

rec

Figure 4

FAST AND LS TTL DATA

5-4