Datasheet SN74LS157M, SN74LS157MEL, SN74LS157ML1, SN74LS157ML2, SN74LS157MR1 Datasheet (MOTOROLA)

 Semiconductor Components Industries, LLC, 1999

December, 1999 – Rev. 6

1 Publication Order Number:

SN74LS157/D

SN74LS157

Quad 2-Input Multiplexer

The LSTTL/MSI SN74LS157 is a high speed Quad 2-Input
Multiplexer. Four bits of data from two sources can be selected using
the common Select and Enable inputs. The four buffered outputs
present the selected data in the true (non-inverted) form. The LS157
can also be used to generate any four of the 16 different functions of
two variables. The LS157 is fabricated with the Schottky barrier diode
process for high speed and is completely compatible with all
ON Semiconductor TTL families.

• Schottky Process for High Speed

• Multifunction Capability

• Non-Inverting Outputs

• Input Clamp Diodes Limit High Speed Termination Effects

• Special Circuitry Ensures Glitch Free Multiplexing

• ESD > 3500 Volts

GUARANTEED OPERATING RANGES

Symbol Parameter Min Typ Max Unit

V

CC

Supply Voltage 4.75 5.0 5.25 V

T

A

Operating Ambient

T emperature Range

0 25 70 °C

I

OH

Output Current – High –0.4 mA

I

OL

Output Current – Low 8.0 mA

LOW

POWER

SCHOTTKY

Device Package Shipping

ORDERING INFORMATION

SN74LS157N 16 Pin DIP 2000 Units/Box
SN74LS157D 16 Pin

SOIC

D SUFFIX

CASE 751B

http://onsemi.com

2500/Tape & Reel

PLASTIC
N SUFFIX
CASE 648

16

1

16

1

SN74LS157

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2

CONNECTION DIAGRAM DIP (TOP VIEW)

Common Select Input
Enable (Active LOW) Input
Data Inputs from Source 0
Data Inputs from Source 1
Multiplexer Outputs

S
E
I0a – I

0d

I1a – I

1d

Za – Z

d

1.0 U.L.

1.0 U.L.

0.5 U.L.

0.5 U.L.
10 U.L.

0.5 U.L.

0.5 U.L.

0.25 U.L.

0.25 U.L.
5 U.L.

NOTES:

a) 1 TTL Unit Load (U.L.) = 40 mA HIGH/1.6 mA LOW.

HIGH LOW

(Note a)LOADING

PIN NAMES

V

CC

= PIN 16

GND = PIN 8

LOGIC SYMBOL

NOTE:
The Flatpak version has the same
pinouts (Connection Diagram) as
the Dual In-Line Package.

14 13 12 11 10 9

123456

7

16 15

8

V

CC

S

E

I0cI

1cZc

I

1d

I

0d

Z

d

I0aI

1dZaI0bI1b

ZbGND

15 2 3 5 6 14 13 11 10

1

4 7 12 9

EI0aI1aI0bI1bI0cI1cI0dI

1d

ZaZbZcZ

d

S

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3

LOGIC DIAGRAM

I

0aI1a

I

0bI1bI0c

I

1cI0d

I1dE S

Z

a

Z

b

Z

c

Z

d

14 126

7

3

4

5

9

11

12

10

13 15

VCC = PIN 16
GND = PIN 8

= PIN NUMBERS

FUNCTIONAL DESCRIPTION

The LS157 is a Quad 2-Input Multiplexer fabricated with
the Schottky barrier diode process for high speed. It selects
four bits of data from two sources under the control of a
common Select Input (S). The Enable Input (E

) is active
LOW. When E is HIGH, all of the outputs (Z) are forced
LOW regardless of all other inputs.

The LS157 is the logic implementation of a 4-pole,
2-position switch where the position of the switch is
determined by the logic levels supplied to the Select Input.
The logic equations for the outputs are:

Za = E ⋅ (I1a ⋅ S + I0a ⋅ S) Zb = E ⋅ (I1b ⋅ S + I0b ⋅ S)
Z

c

= E ⋅ (I1c ⋅ S + I0c ⋅ S)Zd = E ⋅ (I

1d

⋅ S + I0d ⋅ S)

A common use of the LS157 is the moving of data from
two groups of registers to four common output busses. The
particular register from which the data comes is determined
by the state of the Select Input. A less obvious use is as a
function generator. The LS157 can generate any four of the
16 different functions of two variables with one variable
common. This is useful for implementing highly irregular
logic.

TRUTH TABLE

ENABLE

SELECT

INPUT

INPUTS OUTPUT

E S I

0

I

1

Z

H X X X L
L H X LL
L H X HH
L L L XL
L L H X H

H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care

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4

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)

Limits

Symbol Parameter

Min Typ Max

Unit Test Conditions

V

IH

Input HIGH Voltage 2.0 V

Guaranteed Input HIGH Voltage for
All Inputs

V

IL

Input LOW Voltage

0.8
V

Guaranteed Input LOW Voltage for
All Inputs

V

IK

Input Clamp Diode Voltage –0.65 –1.5 V VCC = MIN, IIN = –18 mA

V

OH

Output HIGH Voltage 2.7 3.5 V

VCC = MIN, IOH = MAX, VIN = V

IH

or VIL per Truth Table

p

0.25 0.4 V IOL = 4.0 mA

VCC = VCC MIN,

VOLOutput LOW Voltage

0.35 0.5 V IOL = 8.0 mA

V

IN

=

V

IL

or

V

IH

per Truth Table

I

IH

Input HIGH Current

I

0

, I

1

E, S

20
40

µA VCC = MAX, VIN = 2.7 V

IH

I0, I

1

E, S

0.1

0.2

mA VCC = MAX, VIN = 7.0 V

I

IL

Input LOW Current

I

0

, I

1

E, S

–0.4
–0.8

mA VCC = MAX, VIN = 0.4 V

I

OS

Short Circuit Current (Note 1) –20 –100 mA VCC = MAX

I

CC

Power Supply Current 16 mA VCC = MAX

Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.

AC CHARACTERISTICS (T

A

= 25°C)

Limits

Symbol Parameter

Min Typ Max

Unit Test Conditions

t

PLH

t

PHL

Propagation Delay
Data to Output

9.0

9.0

14
14

ns Figure 2

t

PLH

t

PHL

Propagation Delay
Enable to Output

13
14

20
21

ns Figure 1

VCC = 5.0 V

C

L

= 15 pF

t

PLH

t

PHL

Propagation Delay
Select to Output

15
18

23
27

ns Figure 2

AC WAVEFORMS

Figure 1. Figure 2.

V

IN

V

OUT

1.3 V
t

PHL

1.3 V
t

PLH

1.3 V 1.3 V

V

IN

V

OUT

1.3 V
t

PHL

1.3 V
t

PLH

1.3 V

1.3 V

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P ACKAGE DIMENSIONS

N SUFFIX

PLASTIC PACKAGE

CASE 648–08

ISSUE R

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

–A–

B

F

C

S

H

G

D

J

L

M

16 PL

SEATING

18

916

K

PLANE

–T–

M

A

M

0.25 (0.010) T

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A 0.740 0.770 18.80 19.55
B 0.250 0.270 6.35 6.85
C 0.145 0.175 3.69 4.44
D 0.015 0.021 0.39 0.53
F 0.040 0.70 1.02 1.77
G 0.100 BSC 2.54 BSC
H 0.050 BSC 1.27 BSC
J 0.008 0.015 0.21 0.38
K 0.110 0.130 2.80 3.30
L 0.295 0.305 7.50 7.74
M 0 10 0 10
S 0.020 0.040 0.51 1.01

____

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6

P ACKAGE DIMENSIONS

D SUFFIX

PLASTIC SOIC PACKAGE

CASE 751B–05

ISSUE J

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.

18

16 9

SEATING

PLANE

F

J

M

R

X 45

_

G

8 PLP

–B–

–A–

M

0.25 (0.010) B

S

–T–

D

K

C

16 PL

S

B

M

0.25 (0.010) A

S

T

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A 9.80 10.00 0.386 0.393
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019

F 0.40 1.25 0.016 0.049

G 1.27 BSC 0.050 BSC

J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009
M 0 7 0 7

P 5.80 6.20 0.229 0.244
R 0.25 0.50 0.010 0.019

____

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Notes

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