Page 1
DUAL JK NEGATIVE
OPERATING MODE
EDGE-TRIGGERED FLIP-FLOP
The SN54/74LS112A dual JK flip-flop features individual J, K, clock, and
asynchronous set and clear inputs to each flip-flop. When the clock goes
HIGH, the inputs are enabled and data will be accepted. The logic level of the
J and K inputs may be allowed to change when the clock pulse is HIGH and
the bistable will perform according to the truth table as long as minimum set-up
and hold time are observed. Input data is transferred to the outputs on the
negative-going edge of the clock pulse.
SN54/74LS1 12A
DUAL JK NEGATIVE
EDGE-TRIGGERED FLIP-FLOP
LOW POWER SCHOTTKY
LOGIC DIAGRAM (Each Flip-Flop)
Q
5(9)
CLEAR (C
)
D
15(14)
J
3(11)
1(13)
CLOCK (CP)
MODE SELECT — TRUTH TABLE
INPUTS OUTPUTS
SDC
Set
Reset (Clear)
*Undetermined
Toggle
Load “0” (Reset)
Load “1” (Set)
Hold
* Both outputs will be HIGH while both S
are unpredictable if S
H, h = HIGH Voltage Level
L, I = LOW Voltage Level
X = Don’t Care
l, h (q) = Lower case letters indicate the state of the referenced input (or output)
l, h (q) = one set-up time prior to the HIGH to LOW clock transition.
D
L
H
L
H
H
H
H
and CD go HIGH simultaneously.
D
J K Q Q
D
H
X
X
H
L
X
L
H
H
H
H
and CD are LOW, but the output states
X
X
X
h
h
l
h
h
l
l
l
L
L
H
H
H
q
q
H
L
L
H
q
q
6(7)
4(10)
2(12)
Q
SET (S
K
J SUFFIX
CERAMIC
16
1
)
D
16
1
16
1
CASE 620-09
N SUFFIX
PLASTIC
CASE 648-08
D SUFFIX
SOIC
CASE 751B-03
ORDERING INFORMATION
SN54LSXXXJ Ceramic
SN74LSXXXN Plastic
SN74LSXXXD SOIC
LOGIC SYMBOL
4
S
D
5
J
CP
K
C
D
15
Q
13
6
Q
VCC = PIN 16
GND = PIN 8
3
1
2
12
10
S
11
D
9
Q
J
CP
7
Q
K
C
D
14
FAST AND LS TTL DAT A
5-1
Page 2
SN54/74LS112A
VILI
LOW Volt
V
pg
54
2.5
3.5
V
VOHOutput HIGH Voltage
CC
,
OH
,
IN IH
VOLOutput LOW Volt
V
V
V
IIHI
HIGH C
t
PLH
pg y,
C
L
pF
V
5.0 V
GUARANTEED OPERATING RANGES
Symbol Parameter Min Typ Max Unit
V
CC
T
A
I
OH
I
OL
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Symbol Parameter
V
IH
V
IK
I
IL
I
OS
I
CC
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS (T
Symbol Parameter
f
MAX
t
PLH
t
PHL
AC SETUP REQUIREMENTS (T
Symbol Parameter
t
W
t
W
t
s
t
h
Supply Voltage 54
Operating Ambient Temperature Range 54
Output Current — High 54, 74 –0.4 mA
Output Current — Low 54
Limits
Min Typ Max
Input HIGH Voltage 2.0 V
nput
Input Clamp Diode Voltage –0.65 –1.5 V VCC = MIN, IIN = –18 mA
nput
Input LOW Current J, K
Short Circuit Current (Note 1) –20 –100 mA VCC = MAX
Power Supply Current 6.0 mA VCC = MAX
Maximum Clock Frequency 30 45 MHz
Propagation Delay, Clock
Clear, Set to Output
Clock Pulse Width High 20 ns
Clear, Set Pulse Width 25 ns
Setup Time 20 ns
Hold Time 0 ns
age
age
J, K
Set, Clear
urren
A
Clock
J, K
Set, Clear
Clock
Clear, Set, Clk
= 25°C, VCC = 5.0 V)
= 25°C, VCC = 5.0 V)
A
54 0.7
74 0.8
74 2.7 3.5 V
54, 74 0.25 0.4 V IOL = 4.0 mA
74 0.35 0.5 V IOL = 8.0 mA
Limits
Min Typ Max
15 20 ns
15 20 ns
Limits
Min Typ Max
74
74
74
20
60
80
0.1
0.3
0.4
–0.4
–0.8
4.5
4.75
–55
0
Unit Test Conditions
Guaranteed Input HIGH Voltage for
All Inputs
Guaranteed Input LOW Voltage for
All Inputs
VCC = MIN, IOH = MAX, VIN = V
or VIL per Truth Table
µA VCC = MAX, VIN = 2.7 V
mA VCC = MAX, VIN = 7.0 V
mA VCC = MAX, VIN = 0.4 V
Unit T est Conditions
Unit T est Conditions
5.0
5.0
25
25
VCC = 5.0 V
5.5
5.25
125
70
4.0
8.0
VCC = VCC MIN,
=
IN
IL
per Truth Table
C
= 15
F
= 15
=
CC
or
V
°C
mA
IH
IH
FAST AND LS TTL DATA
5-2
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