Page 1
DUAL JK POSITIVE
OPERATING MODE
EDGE-TRIGGERED FLIP-FLOP
The SN54/74LS109A consists of two high speed completely independent
transition clocked JK
and fall times of the clock waveform. The JK
flip-flop by simply connecting the J and K
flip-flops. The clocking operation is independent of rise
design allows operation as a D
pins together.
SN54/74LS109A
DUAL JK POSITIVE
EDGE-TRIGGERED FLIP-FLOP
LOGIC DIAGRAM
SET (SD)
5(11)
1(15)
CLOCK
4(12)
2(14)
3(13)
)
D
J
K
CLEAR (C
MODE SELECT — TRUTH TABLE
INPUTS OUTPUTS
SDC
Set
Reset (Clear)
*Undetermined
Load “1” (Set)
Hold
Toggle
Load “0” (Reset)
* Both outputs will be HIGH while both S
are unpredictable if S
H, h = HIGH Voltage Level
L, I = LOW Voltage Level
X = Don’t Care
l, h (q) = Lower case letters indicate the state of the referenced input (or output)
l, h (q) = one set-up time prior to the LOW to HIGH clock transition.
D
L
H
L
H
H
H
H
and CD go HIGH simultaneously.
D
J K Q Q
D
H
X
X
H
L
X
L
H
H
H
H
and CD are LOW, but the output states
X
X
X
h
h
l
h
h
l
l
l
L
L
H
H
H
H
L
q
q
q
q
L
H
Q
6(10)
Q
7(9)
LOW POWER SCHOTTKY
J SUFFIX
CERAMIC
16
1
16
1
16
1
CASE 620-09
N SUFFIX
CASE 648-08
D SUFFIX
CASE 751B-03
ORDERING INFORMATION
SN54LSXXXJ Ceramic
SN74LSXXXN Plastic
SN74LSXXXD SOIC
LOGIC SYMBOL
511
6
S
D
J
2
CP
4
K
3
C
D
14
Q
Q
J
12
CP
7
13
K
PLASTIC
SOIC
S
D
Q
Q
C
D
10
9
FAST AND LS TTL DAT A
5-1
1
VCC = PIN 16
GND = PIN 8
15
Page 2
SN54/74LS109A
VILI
LOW Volt
V
pg
54
2.5
3.5
V
VOHOutput HIGH Voltage
CC
,
OH
,
IN IH
VOLOutput LOW Volt
V
V
V
I
IH
PLH
Clock, Cl
t
C
L
pF
t
p
V
5.0 V
GUARANTEED OPERATING RANGES
Symbol Parameter Min Typ Max Unit
V
CC
T
A
I
OH
I
OL
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Symbol Parameter
V
IH
V
IK
I
IH
I
IL
I
OS
I
CC
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS (T
Symbol Parameter
f
MAX
t
PLH
t
PHL
AC SETUP REQUIREMENTS (T
Symbol Parameter
t
W
s
t
h
Supply Voltage 54
Operating Ambient Temperature Range 54
Output Current — High 54, 74 –0.4 mA
Output Current — Low 54
Limits
Min Typ Max
Input HIGH Voltage 2.0 V
nput
Input Clamp Diode Voltage –0.65 –1.5 V VCC = MIN, IIN = –18 mA
Input HIGH Current
J, K, Clock
Set, Clear
J, K, Clock
Set, Clear
Input LOW Current
J, K, Clock
Set, Clear
Output Short Circuit Current (Note 1) –20 –100 mA VCC = MAX
Power Supply Current 8.0 mA VCC = MAX
Maximum Clock Frequency 25 33 MHz
Clock High Clear, Set Pulse Width 25 ns
Data Setup Time — HIGH
Data Setup Time — LOW
Hold time 5.0 ns
age
age
= 25°C, VCC = 5.0 V)
A
ear, Set to Outpu
= 25°C, VCC = 5.0 V)
A
54 0.7
74 0.8
74 2.7 3.5 V
54, 74 0.25 0.4 V IOL = 4.0 mA
74 0.35 0.5 V IOL = 8.0 mA
Limits
Min Typ Max
13 25 ns
25 40 ns
Limits
Min Typ Max
20 ns
20 ns
74
74
74
20
40
0.1
0.2
–0.4
–0.8
4.5
4.75
–55
0
Unit Test Conditions
Guaranteed Input HIGH Voltage for
All Inputs
Guaranteed Input LOW Voltage for
All Inputs
VCC = MIN, IOH = MAX, VIN = V
or VIL per Truth Table
µA VCC = MAX, VIN = 2.7 V
mA VCC = MAX, VIN = 7.0 V
mA VCC = MAX, VIN = 0.4 V
Unit Test Conditions
Unit Test Conditions
5.0
5.0
25
25
5.5
5.25
125
70
4.0
8.0
VCC = VCC MIN,
=
IN
IL
per Truth Table
VCC = 5.0 V
C
= 15
F
= 15
=
CC
or
IH
IH
V
°C
mA
FAST AND LS TTL DATA
5-2
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