Datasheet SN74HC86-Q1 Datasheet (TEXAS INSTRUMENTS)

SN74HC86-Q1

OUTPUT

QUADRUPLE 2-INPUT EXCLUSIVE-OR GATE

SCLS587C − JUNE 2004 − REVISED APRIL 2008

D Qualified for Automotive Applications

D Wide Operating Voltage Range of 2 V to 6 V

D Outputs Can Drive Up To 10 LSTTL Loads

D Low Power Consumption, 20-µA Max I

D ±4-mA Output Drive at 5 V

D Low Input Current of 1 µA Max

D True Logic

CC

D OR PW PACKAGE

(TOP VIEW)

1A

1

1B

2

3

1Y

4

2A

5

2B

6

2Y

GND

7

14

13

12

11

10

V

CC

4B
4A
4Y
3B

9

3A

8

3Y

description/ordering information

This device contains four independent 2-input exclusive-OR gates. They perform the Boolean function
Y = A ę B or Y = A

A common application is as a true/complement element. If one of the inputs is low, the other input is reproduced
in true form at the output. If one of the inputs is high, the signal on the other input is reproduced inverted at the
output.

−40°C to 85°C

−40°C to 125°C

†

For the most current package and ordering information, see the Package Option Addendum at the end of this
document, or see the TI web site at http://www.ti.com.

‡

Package drawings, thermal data, and symbolization are available at http://www.ti.com/packaging.

B + AB in positive logic.

T

A

SOIC − D Reel of 2500 SN74HC86IDRQ1 HC86I

TSSOP − PW Reel of 2000 SN74HC86IPWRQ1 HC86I

SOIC − D Reel of 2500 SN74HC86QDRQ1 HC86Q

TSSOP − PW Reel of 2000 SN74HC86QPWRQ1 HC86Q

ORDERING INFORMATION

PACKAGE

‡

PART NUMBER

{

ORDERABLE

TOP-SIDE
MARKING

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

FUNCTION TABLE

(each gate)

INPUTS

A B

L L L

L HH

H LH

H H L

OUTPUT

Y

Copyright  2008, Texas Instruments Incorporated

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

1

SN74HC86-Q1
QUADRUPLE 2-INPUT EXCLUSIVE-OR GATE

SCLS587C − JUNE 2004 − REVISED APRIL 2008

exclusive-OR logic

An exclusive-OR gate has many applications, some of which can be represented better by alternative logic
symbols.

Exclusive OR

= 1

These are five equivalent exclusive-OR symbols valid for an ’HC86 gate in positive logic; negation may be
shown at any two ports.

Logic Identity Element Even-Parity Element Odd-Parity Element

= 2k 2k + 1

The output is active (low) if
all inputs stand at the same
logic level (i.e., A = B).

The output is active (low) if
an even number of inputs
(i.e., 0 or 2) are active.

The output is active (high) if
an odd number of inputs (i.e.,
only 1 of the 2) are active.

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, VCC −0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input clamp current, I
Output clamp current, I
Continuous output current, I
Continuous current through V
Package thermal impedance, θ

Storage temperature range, T

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

2. The package thermal impedance is calculated in accordance with JESD 51-7.

(VI < 0 or VI > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

IK

(VO < 0 or VO > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

OK

(VO = 0 to VCC) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

O

or GND ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC

(see Note 2): D package 86°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

JA

PW package 113°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

−65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

†

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN74HC86-Q1

VIHHigh level input voltage

V

VILLow level input voltage

V

∆t/∆v

Input transition rise/fall time

ns

PARAMETER

TEST CONDITIONS

V

CC

UNIT

I

OH

µA

V

OH

V

I

V

IH

V

IL

V

I

OL

µA

V

OL

V

I

V

IH

V

IL

V

QUADRUPLE 2-INPUT EXCLUSIVE-OR GATE

SCLS587C − JUNE 2004 − REVISED APRIL 2008

recommended operating conditions (see Note 3)

MIN NOM MAX UNIT

V

V

V

V

V

∆t/∆v Input transition rise/fall time

T

NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,

Supply voltage 2 5 6 V

CC

VCC = 2 V 1.5

V

High-level input voltage

IH

= 4.5 V 3.15

CC

VCC = 6 V 4.2

VCC = 2 V 0.5

V

Low-level input voltage

IL

= 4.5 V 1.35

CC

VCC = 6 V 1.8

Input voltage 0 V

I

Output voltage 0 V

O

VCC = 2 V 1000

V

= 4.5 V 500

CC

VCC = 6 V 400

Operating free-air temperature −40 125 °C

A

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

CC

CC

V

V

V

V

ns

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)

PARAMETER TEST CONDITIONS V

IOH = −20 µA

20

V

OH

VI = VIH or V

or

IL

IOH = −4 mA 4.5 V 3.7 3.84

IOH = −5.2 mA 6 V 5.2 5.34

IOL = 20 µA

20

V

OL

VI = VIH or V

or

IL

IOL = 4 mA 4.5 V 0.4 0.33

IOL = 5.2 mA 6 V 0.4 0.33

I

I

I

CC

C

i

VI = VCC or 0 6 V ±1000 ±1000 nA

VI = VCC or 0, IO = 0 6 V 40 20 µA

2 V to 6 V 10 10 pF

TA = −405C

TO 1255C

MIN MAX MIN MAX

2 V 1.9 1.9

4.5 V 4.4 4.4

6 V 5.9 5.9

2 V 0.1 0.1

4.5 V 0.1 0.1

6 V 0.1 0.1

TA = −405C

TO 855C

UNIT

V

V

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3

SN74HC86-Q1

PARAMETER

V

CC

UNIT

p

tpdA or B

Y

ns

t

QUADRUPLE 2-INPUT EXCLUSIVE-OR GATE

SCLS587C − JUNE 2004 − REVISED APRIL 2008

switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)

PARAMETER

t

d

t

t

FROM

(INPUT) (OUTPUT)

A or B Y

operating characteristics, TA = 25°C

PARAMETER TEST CONDITIONS TYP UNIT

C

Power dissipation capacitance per gate No load 35 pF

pd

TO

TA = −405C

V

TO 1255C

MIN MAX MIN MAX

2 V 150 125

4.5 V 30 25

6 V 25 21

2 V 110 95

Y

4.5 V 22 19

6 V 19 16

TA = −405C

TO 855C

UNIT

ns

ns

Input

NOTES: A. C

B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following

C. The outputs are measured one at a time, with one input transition per measurement.
D. t

PARAMETER MEASUREMENT INFORMATION

From Output

Under Test

LOAD CIRCUIT

90% 90%

t

r

VOLTAGE WAVEFORM

INPUT RISE AND FALL TIMES

includes probe and test-fixture capacitance.

L

characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.

PLH

and t

are the same as tpd.

PHL

Test
Point

C

= 50 pF

L

(see Note A)

In-Phase

V

50%50%

CC

10%10%

0 V

t

f

Out-of-Phase

Figure 1. Load Circuit and Voltage Waveforms

Input

Output

Output

50%

t

t

PLH

PHL

50%

t

PHL

90% 90%

t

r

t

PLH

50% 50%

10% 10%

t

f

VOLTAGE WAVEFORMS

PROPAGATION DELAY AND OUTPUT TRANSITION TIMES

V

CC

0 V

V

50%50%

OH

10%10%

V

OL

t

f

V

OH

90%90%

V

OL

t

r

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM

www.ti.com 26-Mar-2010

PACKAGING INFORMATION

Orderable Device Status

SN74HC86IDRG4Q1 ACTIVE SOIC D 14 2500 Green (RoHS &

SN74HC86IDRQ1 ACTIVE SOIC D 14 2500 Green (RoHS &

SN74HC86IPWRG4Q1 ACTIVE TSSOP PW 14 2000 Green (RoHS &

SN74HC86IPWRQ1 ACTIVE TSSOP PW 14 2000 Green (RoHS &

SN74HC86QDRG4Q1 ACTIVE SOIC D 14 2500 Green (RoHS &

SN74HC86QDRQ1 ACTIVE SOIC D 14 2500 Green (RoHS &

SN74HC86QPWRG4Q1 ACTIVE TSSOP PW 14 2000 Green (RoHS &

SN74HC86QPWRQ1 ACTIVE TSSOP PW 14 2000 Pb-Free

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(1)

Package

Type

Package
Drawing

Pins Package

Qty

Eco Plan

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

(RoHS)

(2)

Lead/Ball Finish MSL Peak Temp

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-250C-UNLIM

(3)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

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OTHER QUALIFIED VERSIONS OF SN74HC86-Q1 :

Catalog: SN74HC86

•

Military: SN54HC86

•

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com 26-Mar-2010

NOTE: Qualified Version Definitions:

Catalog - TI's standard catalog product

•

Military - QML certified for Military and Defense Applications

•

Addendum-Page 2

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