Page 1
SOIC
D
AHC132
40°C to 85°C
D
Operating Range 2-V to 5.5-V V
D
Operation From Very Slow Input
Transitions
D
T emperature-Compensated Threshold
Levels
D
High Noise Immunity
SN54AHC132 ...J OR W PACKAGE
SN74AHC132 . . . D, DB, DGV, N, NS,
OR PW PACKAGE
(TOP VIEW)
1A
1
1B
2
1Y
3
2A
4
2B
5
6
2Y
GND
7
14
13
12
11
10
V
CC
4B
4A
4Y
3B
9
3A
8
3Y
CC
D
D
D
SN74AHC132 . . . RGY PACKAGE
1B
1Y
2A
2B
2Y
(TOP VIEW)
1A
114
2
3
4
5
6
78
GND
CC
V
3Y
SN54AHC132, SN74AHC132
QUADRUPLE POSITIVE-NAND GATES
WITH SCHMITT-TRIGGER INPUTS
SCLS365G – MAY 1997 – REVISED SEPTEMBER 2002
Same Pinouts as ’AHC00
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
13
12
11
10
SN54AHC132 . . . FK PACKAGE
4B
4A
4Y
3B
9
3A
1Y
NC
2A
NC
2B
NC – No internal connection
(TOP VIEW)
1B1ANC
3212019
4
5
6
7
8
910111213
2Y
NC
GND
CC
V
3Y
4B
18
17
16
15
14
3A
4A
NC
4Y
NC
3B
description/ordering information
The ’AHC132 devices are quadruple positive-NAND gates designed for 2-V to 5.5-V VCC operation.
These devices perform the Boolean function Y = A
ORDERING INFORMA TION
T
A
QFN – RGY Tape and reel SN74AHC132RGYR HA132
PDIP – N Tube SN74AHC132N SN74AHC132N
°
–
–55°C to 125°C
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
°
SOP – NS Tape and reel SN74AHC132NSR AHC132
SSOP – DB Tape and reel SN74AHC132DBR HA132
TSSOP – PW Tape and reel SN74AHC132PWR HA132
TVSOP – DGV Tape and reel SN74AHC132DGVR HA132
CDIP – J Tube SNJ54AHC132J SNJ54AHC132J
CFP – W Tube SNJ54AHC132W SNJ54AHC132W
LCCC – FK Tube SNJ54AHC132FK SNJ54AHC132FK
PACKAGE
–
†
Tube SN74AHC132D
Tape and reel SN74AHC132DR
• B or Y = A + B in positive logic.
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 2002, Texas Instruments Incorporated
1
Page 2
SN54AHC132, SN74AHC132
QUADRUPLE POSITIVE-NAND GATES
WITH SCHMITT-TRIGGER INPUTS
SCLS365G – MAY 1997 – REVISED SEPTEMBER 2002
description/ordering information (continued)
Each circuit functions as a NAND gate, but because of the Schmitt action, it has different input threshold levels
for positive- and negative-going signals.
These circuits are temperature compensated and can be triggered from the slowest of input ramps and still give
clean jitter-free output signals.
FUNCTION TABLE
(each gate)
INPUTS
A B
H H L
L XH
X L H
logic diagram, each gate (positive logic)
A
OUTPUT
Y
Y
B
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
Output voltage range, V
Input clamp current, I
Output clamp current, I
Continuous output current, I
Continuous current through V
Package thermal impedance, θ
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
3. The package thermal impedance is calculated in accordance with JESD 51-5.
(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
(see Note 1) –0.5 V to V
O
(V
< 0) –20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IK
I
(V
OK
< 0 or VO > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
(V
= 0 to VCC) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
O
or GND ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
(see Note 2): D package 86°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
(see Note 2): DB package 96°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 2): DGV package 127°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 2): N package 80°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 2): NS package 76°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 2): PW package 113°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 3): RGY package 47°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
CC
+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Page 3
UNIT
mA
mA
PARAMETER
TEST CONDITIONS
V
UNIT
V
T+
V
T
Hysteresis (V
T
V
T
)
SN54AHC132, SN74AHC132
QUADRUPLE POSITIVE-NAND GATES
WITH SCHMITT-TRIGGER INPUTS
SCLS365G – MAY 1997 – REVISED SEPTEMBER 2002
recommended operating conditions (see Note 4)
SN54AHC132 SN74AHC132
MIN MAX MIN MAX
V
V
V
I
OH
I
OL
T
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
input threshold voltage
input threshold voltage
* On products compliant to MIL-PRF-38535, this parameter is not production tested at VCC = 0 V.
Supply voltage 2 5.5 2 5.5 V
CC
Input voltage 0 5.5 0 5.5 V
I
Output voltage 0 V
O
VCC = 2 V –50 –50
High-level output current
Low-level output current
Operating free-air temperature –55 125 –40 85 °C
A
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
Positive-going
–
Negative-going
∆V
T
–
–
+
V
OH
V
OL
I
I
I
CC
C
i
–
IOH = –50 mA
IOH = –4 mA 3 V 2.58 2.48 2.48
IOH = –8 mA 4.5 V 3.94 3.8 3.8
IOL = 50 mA
IOL = 4 mA 3 V 0.36 0.5 0.44
IOL = 8 mA 4.5 V 0.36 0.5 0.44
VI = 5.5 V or GND 0 V to 5.5 V ±0.1 ±1* ±1
VI = VCC or GND, IO = 0 5.5 V 2 20 20
VI = VCC or GND 5 V 1.9 10 10 pF
4.5 V 1.75 3.15 1.75 3.15 1.75 3.15
5.5 V 2.15 3.85 2.15 3.85 2.15 3.85
4.5 V 1.35 2.75 1.35 2.75 1.35 2.75
5.5 V 1.65 3.35 1.65 3.35 1.65 3.35
4.5 V 0.4 1.4 0.4 1.4 0.4 1.4
5.5 V 0.5 1.6 0.5 1.6 0.5 1.6
4.5 V 4.4 4.5 4.4 4.4
4.5 V 0.1 0.1 0.1
VCC = 3.3 V ± 0.3 V
VCC = 5 V ± 0.5 V –8 –8
VCC = 2 V 50 50
VCC = 3.3 V ± 0.3 V
VCC = 5 V ± 0.5 V 8 8
CC
3 V 1.2 2.2 1.2 2.2 1.2 2.2
3 V 0.9 1.9 0.9 1.9 0.9 1.9
3 V 0.3 1.2 0.3 1.2 0.3 1.2
2 V 1.9 2 1.9 1.9
3 V 2.9 3 2.9 2.9
2 V 0.1 0.1 0.1
3 V 0.1 0.1 0.1
TA = 25°C SN54AHC132 SN74AHC132
MIN TYP MAX MIN MAX MIN MAX
CC
–4 –4
4 4
0 V
CC
V
m
A
m
A
V
V
V
V
V
m
A
m
A
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
Page 4
SN54AHC132, SN74AHC132
PARAMETER
UNIT
A or B
Y
C
15 pF
ns
A or B
Y
C
50 pF
ns
PARAMETER
UNIT
A or B
Y
C
15 pF
ns
A or B
Y
C
50 pF
ns
PARAMETER
UNIT
QUADRUPLE POSITIVE-NAND GATES
WITH SCHMITT-TRIGGER INPUTS
SCLS365G – MAY 1997 – REVISED SEPTEMBER 2002
switching characteristics over recommended operating free-air temperature range,
V
= 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
CC
FROM TO LOAD
(INPUT) (OUTPUT) CAPACITANCE
t
PLH
t
PHL
t
PLH
t
PHL
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
p
=
L
p
=
L
switching characteristics over recommended operating free-air temperature range,
V
= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
CC
FROM TO LOAD
(INPUT) (OUTPUT) CAPACITANCE
t
PLH
t
PHL
t
PLH
t
PHL
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
p
=
L
p
=
L
TA = 25°C SN54AHC132 SN74AHC132
MIN TYP MAX MIN MAX MIN MAX
5.6* 11.9* 1* 14* 1 14
5.6* 11.9* 1* 14* 1 14
7.6 15.4 1 17.5 1 17.5
7.6 15.4 1 17.5 1 17.5
TA = 25°C SN54AHC132 SN74AHC132
MIN TYP MAX MIN MAX MIN MAX
3.9* 7.7* 1* 9* 1 9
3.9* 7.7* 1* 9* 1 9
5.3 9.7 1 11 1 11
5.3 9.7 1 11 1 11
noise characteristics, V
V
OL(P)
V
OL(V)
V
OH(V)
V
IH(D)
V
IL(D)
NOTE 5: Characteristics are for surface-mount packages only.
Quiet output, maximum dynamic V
Quiet output, minimum dynamic V
Quiet output, minimum dynamic V
High-level dynamic input voltage 3.5 V
Low-level dynamic input voltage 1.5 V
operating characteristics, V
C
Power dissipation capacitance No load, f = 1 MHz 11 pF
pd
= 5 V, CL = 50 pF, TA = 25°C (see Note 5)
CC
OL
OL
OH
= 5 V, TA = 25°C
CC
PARAMETER TEST CONDITIONS TYP UNIT
SN74AHC132
MIN TYP MAX
0.45 0.8 V
–0.35 –0.8 V
4.8 V
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Page 5
From Output
Under Test
(see Note A)
SN54AHC132, SN74AHC132
QUADRUPLE POSITIVE-NAND GATES
WITH SCHMITT-TRIGGER INPUTS
SCLS365G – MAY 1997 – REVISED SEPTEMBER 2002
PARAMETER MEASUREMENT INFORMATION
V
Test
Point
C
L
From Output
Under Test
(see Note A)
C
L
RL = 1 kΩ
S1
CC
Open
GND
TEST S1
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
Open Drain
Open
V
CC
GND
V
CC
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
Input
Input
t
PLH
In-Phase
Output
t
PHL
Out-of-Phase
Output
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
t
w
50% V
CC
VOLTAGE WAVEFORMS
PULSE DURATION
50% V
CC
50% V
50% V
VOLTAGE WAVEFORMS
50% V
CC
CC
3-STATE AND OPEN-DRAIN OUTPUTS
50% V
LOAD CIRCUIT FOR
V
CC
CC
0 V
V
CC
CC
t
PHL
50% V
t
PLH
50% V
CC
CC
0 V
V
V
V
V
OH
OL
OH
OL
Timing Input
Data Input
Output
Control
Output
Waveform 1
S1 at V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
50% V
t
su
50% V
CC
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
50% V
CC
t
PZL
50% V
50% V
CC
CC
CC
t
PZH
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
CC
t
50% V
50% V
h
CC
CC
t
PLZ
VOL + 0.3 V
t
PHZ
VOH – 0.3 V
V
CC
0 V
V
CC
0 V
V
CC
0 V
≈V
V
OL
V
OH
≈0 V
CC
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
E. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
Page 6
PACKAGE OPTION ADDENDUM
www.ti.com
PACKAGING INFORMATION
Orderable Device Status
SN74AHC132D ACTIVE SOIC D 14 50 Green (RoHS
SN74AHC132DBR ACTIVE SSOP DB 14 2000 Green (RoHS
SN74AHC132DG4 ACTIVE SOIC D 14 50 Green (RoHS
SN74AHC132DGVR ACTIVE TVSOP DGV 14 2000 Green (RoHS
SN74AHC132DR ACTIVE SOIC D 14 2500 Green (RoHS
SN74AHC132DRE4 ACTIVE SOIC D 14 2500 Green (RoHS
SN74AHC132N ACTIVE PDIP N 14 25 Pb-Free
SN74AHC132NE4 ACTIVE PDIP N 14 25 Pb-Free
SN74AHC132NSR ACTIVE SO NS 14 2000 Green (RoHS
SN74AHC132PW ACTIVE TSSOP PW 14 90 Green (RoHS
SN74AHC132PWR ACTIVE TSSOP PW 14 2000 Green (RoHS
SN74AHC132PWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS
SN74AHC132RGYR ACTIVE VQFN RGY 14 3000 Green (RoHS
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Package Type Package
(1)
Drawing
Pins Package
Qty
Eco Plan
(2)
& no Sb/Br)
& no Sb/Br)
& no Sb/Br)
& no Sb/Br)
& no Sb/Br)
& no Sb/Br)
(RoHS)
(RoHS)
& no Sb/Br)
& no Sb/Br)
& no Sb/Br)
& no Sb/Br)
& no Sb/Br)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
CU NIPDAU Level-1-260C-UNLIM -40 to 85 AHC132
CU NIPDAU Level-1-260C-UNLIM -40 to 85 HA132
CU NIPDAU Level-1-260C-UNLIM -40 to 85 AHC132
CU NIPDAU Level-1-260C-UNLIM -40 to 85 HA132
CU NIPDAU Level-1-260C-UNLIM -40 to 85 AHC132
CU NIPDAU Level-1-260C-UNLIM -40 to 85 AHC132
CU NIPDAU N / A for Pkg Type -40 to 85 SN74AHC132N
CU NIPDAU N / A for Pkg Type -40 to 85 SN74AHC132N
CU NIPDAU Level-1-260C-UNLIM -40 to 85 AHC132
CU NIPDAU Level-1-260C-UNLIM -40 to 85 HA132
CU NIPDAU Level-1-260C-UNLIM -40 to 85 HA132
CU NIPDAU Level-1-260C-UNLIM -40 to 85 HA132
CU NIPDAU Level-2-260C-1 YEAR -40 to 85 HA132
10-Jun-2014
Op Temp (°C) Device Marking
(4/5)
Samples
Addendum-Page 1
Page 7
PACKAGE OPTION ADDENDUM
www.ti.com
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
10-Jun-2014
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
Page 8
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
SN74AHC132DBR SSOP DB 14 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1
SN74AHC132DGVR TVSOP DGV 14 2000 330.0 12.4 6.8 4.0 1.6 8.0 12.0 Q1
SN74AHC132DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74AHC132NSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
SN74AHC132PWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74AHC132RGYR VQFN RGY 14 3000 330.0 12.4 3.75 3.75 1.15 8.0 12.0 Q1
Type
Package
Drawing
Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm)B0(mm)K0(mm)P1(mm)W(mm)
Pin1
Quadrant
Pack Materials-Page 1
Page 9
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74AHC132DBR SSOP DB 14 2000 367.0 367.0 38.0
SN74AHC132DGVR TVSOP DGV 14 2000 367.0 367.0 35.0
SN74AHC132DR SOIC D 14 2500 367.0 367.0 38.0
SN74AHC132NSR SO NS 14 2000 367.0 367.0 38.0
SN74AHC132PWR TSSOP PW 14 2000 367.0 367.0 35.0
SN74AHC132RGYR VQFN RGY 14 3000 367.0 367.0 35.0
Pack Materials-Page 2
Page 10
IMPORTANT NOTICE
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changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
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TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
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