Page 1
1
2
3
7
4
5
6
14
13
12
8
11
10
9
1A
1B
1Y
2A
2B
2Y
GND
4B
4A
4Y
3B
3A
V
CC
3Y
SCLS081I – DECEMBER 1982 – REVISED SEPTEMBER 2021
SNx4HC08 Quadruple 2-Input AND Gates
SN74HC08, SN54HC08
1 Features
• Buffered inputs
• Wide operating voltage range: 2 V to 6 V
• Wide operating temperature range:
–40°C to +85°C
• Supports fanout up to 10 LSTTL loads
• Significant power reduction compared to LSTTL
logic ICs
2 Applications
• Combining power good signals
• Enable digital signals
3 Description
This device contains four independent 2-input AND
gates. Each gate performs the Boolean function
Y = A ● B in positive logic.
Device Information
PART NUMBER PACKAGE
SN74HC08D SOIC (14) 8.65 mm × 3.90 mm
SN74HC08DB SSOP (14) 6.30 mm × 5.30 mm
SN74HC08N PDIP (14) 19.34 mm × 6.35 mm
SN74HC08N SO (14) 10.30 mm × 5.30 mm
SN74HC08PW TSSOP (14) 5.00 mm × 4.40 mm
LCCC (14) 1.83 mm × 8.89 mm
SN54HC08
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
CDIP (14) 19.56 mm × 6.67 mm
CFP (14) 9.21 mm × 5.97 mm
(1)
BODY SIZE (NOM)
Functional pinout
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
Page 2
SN74HC08, SN54HC08
SCLS081I – DECEMBER 1982 – REVISED SEPTEMBER 2021
www.ti.com
Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
Pin Functions.................................................................... 3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics - 74..................................... 5
6.6 Electrical Characteristics - 54..................................... 6
6.7 Switching Characteristics - 74.....................................6
6.8 Switching Characteristics - 54.....................................6
6.9 Operating Characteristics........................................... 7
6.10 Typical Characteristics..............................................7
7 Parameter Measurement Information............................ 8
8 Detailed Description........................................................9
8.1 Overview..................................................................... 9
8.2 Functional Block Diagram........................................... 9
8.3 Feature Description.....................................................9
8.4 Device Functional Modes..........................................10
9 Application and Implementation.................................. 11
9.1 Application Information..............................................11
9.2 Typical Application.................................................... 11
10 Power Supply Recommendations..............................13
11 Layout...........................................................................13
11.1 Layout Guidelines................................................... 13
11.2 Layout Example...................................................... 13
12 Device and Documentation Support..........................14
12.1 Documentation Support.......................................... 14
12.2 Support Resources................................................. 14
12.3 Trademarks.............................................................14
12.4 Electrostatic Discharge Caution..............................14
12.5 Glossary..................................................................14
13 Mechanical, Packaging, and Orderable
Information.................................................................... 14
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision H (April 2021) to Revision I (September 2021) Page
• Removed Schmitt-Trigger inputs from the pinout image on the first page..........................................................1
Changes from Revision G (June 2016) to Revision H (April 2021) Page
• Updated the numbering format for tables, figures, and cross-references throughout the document..................1
• Updated to new data sheet standards................................................................................................................ 1
• Increased D (86 to 133.6), DB (106.8 to 113.1), NS (76 to 122.6), and PW (113 to 151.7); decreased N (80 to
66) °C/W............................................................................................................................................................. 5
Changes from Revision F (January 2007) to Revision G (June 2016) Page
• Added ESD Ratings table,Feature Descriptionsection, Device Functional Modes, Application and
Implementation section, Power Supply Recommendationssection, Layoutsection, Device and Documentation
Support section, andMechanical, Packaging, and Orderable Information section........................................... 14
• Removed Ordering Information table, see POA at the end of the datasheet................................................... 14
2 Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: SN74HC08 SN54HC08
Page 3
1
2
3
7
4
5
6
14
13
12
8
11
10
9
1A
1B
1Y
2A
2B
2Y
GND
4B
4A
4Y
3B
3A
V
CC
3Y
4
5
6
7
8
3 2 1 20 19
18
17
16
15
14
9 10 11 12 13
1Y
NC
2A
NC
2B
1B 1A NC VCC4B
2Y
GND NC 3Y 3A
4A
NC
4Y
NC
3B
www.ti.com
5 Pin Configuration and Functions
D, DB, N, PW, J, or W Package
14-Pin SOIC, SSOP, PDIP, TSSOP, CDIP, or CFP
Top View
Pin Functions
PIN
NAME
D, DB, N,
PW, J, or W
FK
1A 1 2 Input Channel 1, Input A
1B 2 3 Input Channel 1, Input B
1Y 3 4 Output Channel 1, Output Y
2A 4 6 Input Channel 2, Input A
2B 5 8 Input Channel 2, Input B
2Y 6 9 Output Channel 2, Output Y
GND 7 10 — Ground
3Y 8 12 Output Channel 3, Output Y
3A 9 13 Input Channel 3, Input A
3B 10 14 Input Channel 3, Input B
4Y 11 16 Output Channel 4, Output Y
4A 12 18 Input Channel 4, Input A
4B 13 19 Input Channel 4, Input B
V
NC
CC
14 20 — Positive Supply
1, 5, 7, 11, 15,
17
I/O DESCRIPTION
— Not internally connected
SCLS081I – DECEMBER 1982 – REVISED SEPTEMBER 2021
SN74HC08, SN54HC08
FK Package
20-Pin LCCC
Top View
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: SN74HC08 SN54HC08
Submit Document Feedback
3
Page 4
SN74HC08, SN54HC08
SCLS081I – DECEMBER 1982 – REVISED SEPTEMBER 2021
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
V
CC
I
IK
I
OK
I
O
T
J
T
stg
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated
under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) Guaranteed by design.
Supply voltage –0.5 7 V
Input clamp current
Output clamp current
(2)
(2)
Continuous output current VO = 0 to V
Continuous current through VCC or GND ±50 mA
Junction temperature
(3)
Storage temperature –60 150 °C
6.2 ESD Ratings
Human-body model (HBM), per ANSI/ESDA/
V
(ESD)
Electrostatic discharge
JEDEC JS-001
Charged-device model (CDM), per JEDEC
specification JESD22-C101
(1)
MIN MAX UNIT
VI < 0 or VI > V
CC
±20 mA
VO < 0 ±20 mA
CC
±25 mA
150 °C
VALUE UNIT
(1)
(2)
±2000
±1000
www.ti.com
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)1
MIN NOM MAX UNIT
V
CC
V
IH
V
IL
V
I
V
O
Δt/Δv Input transition rise and fall rate
T
A
1. All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See
Supply voltage 2 5 6 V
VCC = 2 V 1.5
High-level input voltage
VCC = 6 V 4.2
VCC = 2 V 0.5
Low-level input voltage
VCC = 6 V 1.8
Input voltage 0 V
Output voltage 0 V
VCC = 2 V 1000
VCC = 6 V 400
Operating free-air temperature
SN54HC08 –55 125
SN74HC08 –40 85
Implications of Slow or Floating CMOS Inputs, .
CC
CC
VVCC = 4.5 V 3.15
VVCC = 4.5 V 1.35
V
V
nsVCC = 4.5 V 500
°C
4 Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: SN74HC08 SN54HC08
Page 5
www.ti.com
SCLS081I – DECEMBER 1982 – REVISED SEPTEMBER 2021
6.4 Thermal Information
SN74HC08, SN54HC08
SN74HC08
THERMAL METRIC
(1)
UNITD (SOIC) DB (SSOP) N (CFP) NS (SO) PW (TSSOP)
14 PINS 14 PINS 14 PINS 14 PINS 14 PINS
Junction-to-ambient thermal
R
θJA
resistance
R
Junction-to-case (top) thermal
θ
resistance
JC(top)
Junction-to-board thermal
R
θJB
resistance
Junction-to-top characterization
Ψ
JT
parameter
Junction-to-board
Ψ
JB
characterization parameter
R
Junction-to-case (bottom)
θ
thermal resistance
JC(bot)
133.6 113.1 66.0 122.6 151.7 °C/W
89 62.8 53.7 81.8 79.4 °C/W
89.5 63.4 45.7 83.8 94.7 °C/W
45.5 22.3 33.3 45.4 25.2 °C/W
89.1 62.7 45.5 83.4 94.1 °C/W
N/A N/A N/A N/A N/A °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics - 74
over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted).
Operating free-air temperature (TA)
PARAMETER TEST CONDITIONS V
IOH = -20 µA
OH
High-level
output voltage
V
VI = V
or V
IH
IL
IOH = -4 mA 4.5 V 3.98 4.3 3.84
IOH = -5.2 mA 6 V 5.48 5.8 5.34
IOL = 20 µA
OL
Low-level output
voltage
V
VI = V
or V
IH
IOL = 20 µA 6 V 0.001 0.1 0.1
IL
IOL = 4 mA 4.5 V 0.17 0.26 0.33
IOL = 5.2 mA 6 V 0.15 0.26 0.33
I
CC
i
Input leakage
current
Supply current
Input
capacitance
VI = VCC or 0 6 V ±0.1 ±1 µA
VI = V
CC
or 0
IO = 0 6 V 2 20 µA
I
I
C
CC
MIN TYP MAX MIN TYP MAX
2 V 1.9 1.998 1.9
4.5 V 4.4 4.499 4.4
6 V 5.9 5.999 5.9
2 V 0.002 0.1 0.1
4.5 V 0.001 0.1 0.1
2 V to 6 V 3 10 10 pF
UNIT25°C -40°C to 85°C
V
V
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: SN74HC08 SN54HC08
Submit Document Feedback
5
Page 6
SN74HC08, SN54HC08
SCLS081I – DECEMBER 1982 – REVISED SEPTEMBER 2021
6.6 Electrical Characteristics - 54
over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted).
Operating free-air temperature (TA)
PARAMETER TEST CONDITIONS V
IOH = –20
µA
High-level
V
OH
output voltage
VI = VIH or
V
IL
IOH = –4
mA
IOH = –5.2
mA
IOL = 20
µA
Low-level output
V
OL
voltage
VI = VIH or
V
IL
IOL = 4 mA 4.5 V 0.17 0.26 0.33 0.4
IOL = 5.2
mA
Input leakage
I
I
current
ICCSupply current
Input
C
i
capacitance
VI = VCC or 0 6 V ±0.1 ±1 ±1 µA
VI = VCC or
0
IO = 0 6 V 2 20 40 µA
CC
MIN TYP MAX MIN TYP MAX MIN TYP MAX
2 V 1.9 1.998 1.9 1.9
4.5 V 4.4 4.499 4.4 4.4
6 V 5.9 5.999 5.9 5.9
4.5 V 3.98 4.3 3.84 3.7
6 V 5.48 5.8 5.34 5.2
2 V 0.002 0.1 0.1 0.1
4.5 V 0.001 0.1 0.1 0.1
6 V 0.001 0.1 0.1 0.1
6 V 0.15 0.26 0.33 0.4
2 V to
6 V
3 10 10 10 pF
www.ti.com
UNIT25°C –40°C to 85°C –55°C to 125°C
V
V
6.7 Switching Characteristics - 74
over operating free-air temperature range (unless otherwise noted)
Operating free-air temperature (TA)
PARAMETER FROM TO V
t
t
Propagation delay A or B Y
pd
Transition-time Y
t
CC
MIN TYP MAX MIN TYP MAX
2 V 50 100 125
6 V 8 17 24
2 V 38 75 95
6 V 6 13 16
6.8 Switching Characteristics - 54
over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted).
Operating free-air temperature (TA)
PARAMETER FROM TO V
t
Propagation delay A or B Y
pd
t
Transition-time Y
t
CC
MIN TYP MAX MIN TYP MAX MIN TYP MAX
2 V 50 100 125 150
6 V 8 17 24 25
2 V 38 75 95 110
6 V 6 13 16 19
UNIT25°C –40°C to 85°C
ns4.5 V 10 20 25
ns4.5 V 8 15 19
UNIT25°C –40°C to 85°C –55°C to 125°C
ns4.5 V 10 20 25 30
ns4.5 V 8 15 19 22
6 Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: SN74HC08 SN54HC08
Page 7
IOH Output High Current (mA)
V
OH
Output High Voltage (V)
0 1 2 3 4 5 6
0
1
2
3
4
5
6
7
2-V
4.5-V
6-V
IOL Output Low Current (mA)
V
OL
Output Low Voltage (V)
0 1 2 3 4 5 6
0
0.05
0.1
0.15
0.2
0.25
0.3
2-V
4.5-V
6-V
www.ti.com
SCLS081I – DECEMBER 1982 – REVISED SEPTEMBER 2021
6.9 Operating Characteristics
SN74HC08, SN54HC08
over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted).
PARAMETER TEST CONDITIONS V
Power dissipation capacitance
C
pd
per gate
CC
No load 2 V to 6 V 20 pF
MIN TYP MAX UNIT
6.10 Typical Characteristics
TA = 25°C
Figure 6-1. Typical output voltage in the high state
(VOH)
Copyright © 2021 Texas Instruments Incorporated
Figure 6-2. Typical output voltage in the low state
Product Folder Links: SN74HC08 SN54HC08
(VOL)
Submit Document Feedback
7
Page 8
C
L
(1)
From Output
Under Test
Test
Point
V
OH
V
OL
Output
V
CC
0 V
Input
t
f
(1)
t
r
(1)
90%
10%
90%
10%
t
(1)
90%
10%
t
(1)
90%
10%
50%Input 50%
V
CC
0 V
50% 50%
V
OH
V
OL
t
PLH
(1)
t
PHL
(1)
V
OH
V
OL
t
PHL
(1)
t
PLH
(1)
Output
Output 50% 50%
SN74HC08, SN54HC08
SCLS081I – DECEMBER 1982 – REVISED SEPTEMBER 2021
www.ti.com
7 Parameter Measurement Information
• Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators
having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tt < 6 ns.
• The outputs are measured one at a time, with one input transition per measurement.
A. CL= 50 pF and includes probe and jig capacitance.
Figure 7-1. Load Circuit
A. tt is the greater of tr and tf.
Figure 7-2. Voltage Waveforms Transition Times
A. The maximum between t
8 Submit Document Feedback
PLH
and t
is used for tpd.
PHL
Figure 7-3. Voltage Waveforms Propagation Delays
Product Folder Links: SN74HC08 SN54HC08
Copyright © 2021 Texas Instruments Incorporated
Page 9
xA
xB
xY
www.ti.com
SCLS081I – DECEMBER 1982 – REVISED SEPTEMBER 2021
SN74HC08, SN54HC08
8 Detailed Description
8.1 Overview
This device contains four independent 2-input AND gates. Each gate performs the Boolean function Y = A ● B in
positive logic.
8.2 Functional Block Diagram
8.3 Feature Description
8.3.1 Balanced CMOS Push-Pull Outputs
A balanced output allows the device to sink and source similar currents. The drive capability of this device
may create fast edges into light loads so routing and load conditions should be considered to prevent ringing.
Additionally, the outputs of this device are capable of driving larger currents than the device can sustain without
being damaged. It is important for the output power of the device to be limited to avoid damage due to
over-current. The electrical and thermal limits defined in the Absolute Maximum Ratings must be followed at all
times.
The SN74HC08 can drive a load with a total capacitance less than or equal to the maximum load listed in the
Electrical Characteristics - 74 connected to a high-impedance CMOS input while still meeting all of the datasheet
specifications. Larger capacitive loads can be applied, however it is not recommended to exceed the provided
load value. If larger capacitive loads are required, it is recommended to add a series resistor between the output
and the capacitor to limit output current to the values given in the Absolute Maximum Ratings.
8.3.2 Standard CMOS Inputs
Standard CMOS inputs are high impedance and are typically modeled as a resistor from the input to ground
in parallel with the input capacitance given in the Electrical Characteristics - 74. The worst case resistance is
calculated with the maximum input voltage, given in the Absolute Maximum Ratings, and the maximum input
leakage current, given in the Electrical Characteristics - 74, using ohm's law (R = V ÷ I).
Signals applied to the inputs need to have fast edge rates, as defined by the input transition time in the
Recommended Operating Conditions to avoid excessive current consumption and oscillations. If a slow or noisy
input signal is required, a device with a Schmitt-trigger input should be used to condition the input signal prior to
the standard CMOS input.
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: SN74HC08 SN54HC08
Submit Document Feedback
9
Page 10
GND
Logic
V
CC
Device
-I
IK
+I
IK
+I
OK
-I
OK
SN74HC08, SN54HC08
SCLS081I – DECEMBER 1982 – REVISED SEPTEMBER 2021
www.ti.com
8.3.3 Clamp Diode Structure
The inputs and outputs to this device have both positive and negative clamping diodes as depicted in Figure 8-1.
CAUTION
Voltages beyond the values specified in the Absolute Maximum Ratings table can cause damage to
the device. The recommended input and output voltage ratings may be exceeded if the input and
output clamp-current ratings are observed.
Figure 8-1. Electrical Placement of Clamping Diodes for Each Input and Output
8.4 Device Functional Modes
Table 8-1. Function Table
INPUTS OUTPUT
A B Y
H H H
L X L
X L L
10 Submit Document Feedback
Product Folder Links: SN74HC08 SN54HC08
Copyright © 2021 Texas Instruments Incorporated
Page 11
OC
PG
ON/OF F
RESET
Power Supply
Motor Con troller
On/Off Switch
Over
Temp
Detection
Over Current
Detection
OT
www.ti.com
SCLS081I – DECEMBER 1982 – REVISED SEPTEMBER 2021
9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
In this application, three 2-input AND gates are combined to produce a 4-input AND gate function as shown in
Figure 9-1. The fourth gate can be used for another application in the system, or the inputs can be grounded and
the channel left unused.
This device is used to directly control the RESET pin of a motor controller. The controller requires four input
signals to all be HIGH before being enabled, and should be disabled in the event that any one signal goes LOW.
The 4-input AND gate function combines the four individual reset signals into a single active-low reset signal.
9.2 Typical Application
SN74HC08, SN54HC08
Figure 9-1. Typical application schematic
9.2.1 Design Requirements
9.2.1.1 Power Considerations
Ensure the desired supply voltage is within the range specified in the Recommended Operating Conditions. The
supply voltage sets the device's electrical characteristics as described in the Electrical Characteristics - 74.
The supply must be capable of sourcing current equal to the total current to be sourced by all outputs of the
SN74HC08 plus the maximum supply current, ICC, listed in the Electrical Characteristics - 74. The logic device
can only source or sink as much current as it is provided at the supply and ground pins, respectively. Be sure not
to exceed the maximum total current through GND or VCC listed in the Absolute Maximum Ratings.
Total power consumption can be calculated using the information provided in CMOS Power Consumption and
Cpd Calculation.
Thermal increase can be calculated using the information provided in Thermal Characteristics of Standard Linear
and Logic (SLL) Packages and Devices.
The maximum junction temperature, TJ(max) listed in the Absolute Maximum Ratings, is an
additional limitation to prevent damage to the device. Do not violate any values listed in the Absolute
Maximum Ratings. These limits are provided to prevent damage to the device.
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: SN74HC08 SN54HC08
CAUTION
Submit Document Feedback
11
Page 12
OC
PG
ON/OFF
OT
RESET
SN74HC08, SN54HC08
SCLS081I – DECEMBER 1982 – REVISED SEPTEMBER 2021
www.ti.com
9.2.1.2 Input Considerations
Unused inputs must be terminated to either VCC or ground. These can be directly terminated if the input is
completely unused, or they can be connected with a pull-up or pull-down resistor if the input is to be used
sometimes, but not always. A pull-up resistor is used for a default state of HIGH, and a pull-down resistor is
used for a default state of LOW. The resistor size is limited by drive current of the controller, leakage current into
the SN74HC08, as specified in the Electrical Characteristics - 74, and the desired input transition rate. A 10-kΩ
resistor value is often used due to these factors.
The SN74HC08 has standard CMOS inputs, so input signal edge rates cannot be slow. Slow input edge
rates can cause oscillations and damaging shoot-through current. The recommended rates are defined in the
Recommended Operating Conditions.
Refer to Section 8.3 for additional information regarding the inputs for this device.
9.2.1.3 Output Considerations
The positive supply voltage is used to produce the output HIGH voltage. Drawing current from the output will
decrease the output voltage as specified by the VOH specification in the Electrical Characteristics - 74. Similarly,
the ground voltage is used to produce the output LOW voltage. Sinking current into the output will increase the
output voltage as specified by the VOL specification in the Electrical Characteristics - 74.
Unused outputs can be left floating. Do not connect outputs directly to VCC or ground.
Refer to Section 8.3 for additional information regarding the outputs for this device.
9.2.2 Detailed Design Procedure
1. Add a decoupling capacitor from VCC to GND. The capacitor needs to be placed physically close to the
device and electrically close to both the VCC and GND pins. An example layout is shown in Section 11.
2. Ensure the capacitive load at the output is ≤ 70 pF. This is not a hard limit, however it will ensure optimal
performance. This can be accomplished by providing short, appropriately sized traces from the SN74HC08
to the receiving device.
3. Ensure the resistive load at the output is larger than (VCC / IO(max)) Ω. This will ensure that the maximum
output current from the Absolute Maximum Ratings is not violated. Most CMOS inputs have a resistive load
measured in megaohms; much larger than the minimum calculated above.
4. Thermal issues are rarely a concern for logic gates, however the power consumption and thermal increase
can be calculated using the steps provided in the application report, CMOS Power Consumption and Cpd
Calculation
9.2.3 Application Curves
Figure 9-2. Typical application timing diagram
12 Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: SN74HC08 SN54HC08
Page 13
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1A
1B
2A
2B
2Y
GND V
CC
4B
4A
3B
3A
3Y
GND
V
CC
4Y
1Y
0.1 F
Unused
inputs tied to
V
CC
Bypass capacitor
placed close to the
device
Avoid 90°
corners for
signal lines
Recommend GND flood fill for
improved signal isolation, noise
reduction, and thermal dissipation
Unused
output left
floating
www.ti.com
SCLS081I – DECEMBER 1982 – REVISED SEPTEMBER 2021
10 Power Supply Recommendations
SN74HC08, SN54HC08
The power supply can be any voltage between the minimum and maximum supply voltage rating located in
the Recommended Operating Conditions. Each VCC terminal should have a bypass capacitor to prevent power
disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps
to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The
bypass capacitor should be installed as close to the power terminal as possible for best results, as shown in
Figure 11-1.
11 Layout
11.1 Layout Guidelines
When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many
cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of
a triple-input AND gate are used. Such unused input pins must not be left unconnected because the undefined
voltages at the outside connections result in undefined operational states. All unused inputs of digital logic
devices must be connected to a logic high or logic low voltage, as defined by the input voltage specifications, to
prevent them from floating. The logic level that must be applied to any particular unused input depends on the
function of the device. Generally, the inputs are tied to GND or VCC, whichever makes more sense for the logic
function or is more convenient.
11.2 Layout Example
Copyright © 2021 Texas Instruments Incorporated
Figure 11-1. Example layout for the SN74HC08
Product Folder Links: SN74HC08 SN54HC08
Submit Document Feedback
13
Page 14
SN74HC08, SN54HC08
SCLS081I – DECEMBER 1982 – REVISED SEPTEMBER 2021
www.ti.com
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
• HCMOS Design Considerations
• CMOS Power Consumption and CPD Calculation
• Designing with Logic
12.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.5 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
14 Submit Document Feedback
Copyright © 2021 Texas Instruments Incorporated
Product Folder Links: SN74HC08 SN54HC08
Page 15
PACKAGE OPTION ADDENDUM
www.ti.com
PACKAGING INFORMATION
Orderable Device Status
5962-8404701VCA ACTIVE CDIP J 14 1 Non-RoHS
5962-8404701VDA ACTIVE CFP W 14 25 Non-RoHS
84047012A ACTIVE LCCC FK 20 1 Non-RoHS
8404701CA ACTIVE CDIP J 14 1 Non-RoHS
8404701DA ACTIVE CFP W 14 1 Non-RoHS
JM38510/65203B2A ACTIVE LCCC FK 20 1 Non-RoHS
JM38510/65203BCA ACTIVE CDIP J 14 1 Non-RoHS
JM38510/65203BDA ACTIVE CFP W 14 1 Non-RoHS
M38510/65203B2A ACTIVE LCCC FK 20 1 Non-RoHS
M38510/65203BCA ACTIVE CDIP J 14 1 Non-RoHS
M38510/65203BDA ACTIVE CFP W 14 1 Non-RoHS
SN54HC08J ACTIVE CDIP J 14 1 Non-RoHS
SN74HC08D ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC08
SN74HC08DBR ACTIVE SSOP DB 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC08
SN74HC08DE4 ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC08
SN74HC08DG4 ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC08
Package Type Package
(1)
Drawing
Pins Package
Qty
Eco Plan
(2)
& Green
& Green
& Green
& Green
& Green
& Green
& Green
& Green
& Green
& Green
& Green
& Green
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
SNPB N / A for Pkg Type -55 to 125 5962-8404701VC
A
SNV54HC08J
SNPB N / A for Pkg Type -55 to 125 5962-8404701VD
A
SNV54HC08W
SNPB N / A for Pkg Type -55 to 125 84047012A
SNJ54HC
08FK
SNPB N / A for Pkg Type -55 to 125 8404701CA
SNJ54HC08J
SNPB N / A for Pkg Type -55 to 125 8404701DA
SNJ54HC08W
SNPB N / A for Pkg Type -55 to 125 JM38510/
65203B2A
SNPB N / A for Pkg Type -55 to 125 JM38510/
65203BCA
SNPB N / A for Pkg Type -55 to 125 JM38510/
65203BDA
SNPB N / A for Pkg Type -55 to 125 JM38510/
65203B2A
SNPB N / A for Pkg Type -55 to 125 JM38510/
65203BCA
SNPB N / A for Pkg Type -55 to 125 JM38510/
65203BDA
SNPB N / A for Pkg Type -55 to 125 SN54HC08J
13-Jul-2022
Samples
(4/5)
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Addendum-Page 1
Page 16
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device Status
Package Type Package
(1)
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
SN74HC08DR ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 85 HC08
SN74HC08DRG4 ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC08
SN74HC08DT ACTIVE SOIC D 14 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC08
SN74HC08DTE4 ACTIVE SOIC D 14 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC08
SN74HC08N ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 SN74HC08N
SN74HC08NE4 ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 SN74HC08N
SN74HC08NSR ACTIVE SO NS 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC08
SN74HC08NSRG4 ACTIVE SO NS 14 2000 TBD Call TI Call TI -40 to 85
SN74HC08PW ACTIVE TSSOP PW 14 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC08
SN74HC08PWG4 ACTIVE TSSOP PW 14 90 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC08
SN74HC08PWR ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 85 HC08
SN74HC08PWRG4 ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC08
SN74HC08PWT ACTIVE TSSOP PW 14 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HC08
SNJ54HC08FK ACTIVE LCCC FK 20 1 Non-RoHS
SNPB N / A for Pkg Type -55 to 125 84047012A
& Green
SNJ54HC08J ACTIVE CDIP J 14 1 Non-RoHS
SNPB N / A for Pkg Type -55 to 125 8404701CA
& Green
SNJ54HC08W ACTIVE CFP W 14 1 Non-RoHS
SNPB N / A for Pkg Type -55 to 125 8404701DA
& Green
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
SNJ54HC
08FK
SNJ54HC08J
SNJ54HC08W
13-Jul-2022
Samples
(4/5)
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Addendum-Page 2
Page 17
PACKAGE OPTION ADDENDUM
www.ti.com
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN54HC08, SN54HC08-SP, SN74HC08 :
Catalog : SN74HC08, SN54HC08
•
13-Jul-2022
Automotive : SN74HC08-Q1, SN74HC08-Q1
•
Military : SN54HC08
•
Space : SN54HC08-SP
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 3
Page 18
PACKAGE OPTION ADDENDUM
www.ti.com
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Military - QML certified for Military and Defense Applications
•
Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application
•
13-Jul-2022
Addendum-Page 4
Page 19
PACKAGE MATERIALS INFORMATION
Reel Width (W1)
REEL DIMENSIONS
A0
B0
K0
W
Dimension designed to accommodate the component length
Dimension designed to accommodate the component thickness
Overall width of the carrier tape
Pitch between successive cavity centers
Dimension designed to accommodate the component width
TAPE DIMENSIONS
K0 P1
B0
W
A0
Cavity
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Pocket Quadrants
Sprocket Holes
Q1
Q1Q2 Q2
Q3 Q3Q4 Q4
User Direction of Feed
P1
Reel
Diameter
www.ti.com 15-Aug-2022
TAPE AND REEL INFORMATION
*All dimensions are nominal
SN74HC08DBR SSOP DB 14 2000 330.0 16.4 8.35 6.6 2.4 12.0 16.0 Q1
SN74HC08DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74HC08DR SOIC D 14 2500 330.0 16.4 6.6 9.3 2.1 8.0 16.0 Q1
SN74HC08DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74HC08DR SOIC D 14 2500 330.0 16.8 6.5 9.5 2.1 8.0 16.0 Q1
SN74HC08DRG4 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74HC08DRG4 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74HC08DT SOIC D 14 250 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74HC08NSR SO NS 14 2000 330.0 16.4 8.45 10.55 2.5 12.0 16.2 Q1
SN74HC08PWR TSSOP PW 14 2000 330.0 12.4 6.85 5.45 1.6 8.0 12.0 Q1
SN74HC08PWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74HC08PWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74HC08PWRG4 TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74HC08PWT TSSOP PW 14 250 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
Device Package
Type
Package
Drawing
Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm)B0(mm)K0(mm)P1(mm)W(mm)
Pin1
Quadrant
Pack Materials-Page 1
Page 20
PACKAGE MATERIALS INFORMATION
TAPE AND REEL BOX DIMENSIONS
Width (mm)
W
L
H
www.ti.com 15-Aug-2022
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74HC08DBR SSOP DB 14 2000 356.0 356.0 35.0
SN74HC08DR SOIC D 14 2500 340.5 336.1 32.0
SN74HC08DR SOIC D 14 2500 366.0 364.0 50.0
SN74HC08DR SOIC D 14 2500 367.0 367.0 38.0
SN74HC08DR SOIC D 14 2500 364.0 364.0 27.0
SN74HC08DRG4 SOIC D 14 2500 356.0 356.0 35.0
SN74HC08DRG4 SOIC D 14 2500 340.5 336.1 32.0
SN74HC08DT SOIC D 14 250 210.0 185.0 35.0
SN74HC08NSR SO NS 14 2000 367.0 367.0 38.0
SN74HC08PWR TSSOP PW 14 2000 366.0 364.0 50.0
SN74HC08PWR TSSOP PW 14 2000 364.0 364.0 27.0
SN74HC08PWR TSSOP PW 14 2000 356.0 356.0 35.0
SN74HC08PWRG4 TSSOP PW 14 2000 356.0 356.0 35.0
SN74HC08PWT TSSOP PW 14 250 356.0 356.0 35.0
Pack Materials-Page 2
Page 21
PACKAGE MATERIALS INFORMATION
www.ti.com 15-Aug-2022
TUBE
T - Tube
height
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
5962-8404701VDA W CFP 14 25 506.98 26.16 6220 NA
84047012A FK LCCC 20 1 506.98 12.06 2030 NA
8404701DA W CFP 14 1 506.98 26.16 6220 NA
JM38510/65203B2A FK LCCC 20 1 506.98 12.06 2030 NA
JM38510/65203BDA W CFP 14 1 506.98 26.16 6220 NA
M38510/65203B2A FK LCCC 20 1 506.98 12.06 2030 NA
M38510/65203BDA W CFP 14 1 506.98 26.16 6220 NA
SN74HC08D D SOIC 14 50 506.6 8 3940 4.32
SN74HC08D D SOIC 14 50 507 8 3940 4.32
SN74HC08DE4 D SOIC 14 50 507 8 3940 4.32
SN74HC08DE4 D SOIC 14 50 506.6 8 3940 4.32
SN74HC08DG4 D SOIC 14 50 506.6 8 3940 4.32
SN74HC08DG4 D SOIC 14 50 507 8 3940 4.32
SN74HC08N N PDIP 14 25 506 13.97 11230 4.32
SN74HC08N N PDIP 14 25 506 13.97 11230 4.32
SN74HC08NE4 N PDIP 14 25 506 13.97 11230 4.32
SN74HC08NE4 N PDIP 14 25 506 13.97 11230 4.32
SN74HC08PW PW TSSOP 14 90 530 10.2 3600 3.5
SN74HC08PWG4 PW TSSOP 14 90 530 10.2 3600 3.5
SNJ54HC08FK FK LCCC 20 1 506.98 12.06 2030 NA
SNJ54HC08W W CFP 14 1 506.98 26.16 6220 NA
L - Tube length
Pack Materials-Page 3
Page 22
Page 23
Page 24
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,65
28
1
2,00 MAX
0,38
0,22
15
14
A
0,05 MIN
0,15
M
5,60
5,00
Seating Plane
8,20
7,40
0,10
0,25
0,09
0°–ā8°
Gage Plane
0,25
0,95
0,55
PINS **
DIM
A MAX
A MIN
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
14
6,50
6,50
5,905,90
2016
7,50
6,90
24
8,50
28
10,50
9,907,90
30
10,50
9,90
38
12,90
12,30
4040065 /E 12/01
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Page 25
Page 26
Page 27
Page 28
PACKAGE OUTLINE
12X .100
[2.54]
PIN 1 ID
(OPTIONAL)
1
14
A
-.785.754
-19.9419.15[ ]
SCALE 0.900
4X .005 MIN
14X -.065.045
[0.13]
-1.651.15[ ]
CDIP - 5.08 mm max heightJ0014A
CERAMIC DUAL IN LINE PACKAGE
TYP-.060.015
-1.520.38[ ]
14X -.026.014
-0.660.36[ ]
.010 [0.25] C A B
7
B -.283.245
NOTES:
1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in brackets or parenthesis are for
reference only. Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This package is hermitically sealed with a ceramic lid using glass frit.
4. Index point is provided on cap for terminal identification only and on press ceramic glass frit seal only.
5. Falls within MIL-STD-1835 and GDIP1-T14.
-7.196.22[ ]
-.314.308
-7.977.83[ ]
AT GAGE PLANE
-15
0
TYP
8
.015 GAGE PLANE
[0.38]
14X .008-.014
[0.2-0.36]
.2 MAX TYP
[5.08]
C
.13 MIN TYP
[3.3]
SEATING PLANE
4214771/A 05/2017
www.ti.com
Page 29
SEE DETAIL A
(.300 ) TYP
[7.62]
EXAMPLE BOARD LAYOUT
CDIP - 5.08 mm max heightJ0014A
CERAMIC DUAL IN LINE PACKAGE
SEE DETAIL B
12X (.100 )
[2.54]
14X ( .039)
[1]
1
7
SYMM
LAND PATTERN EXAMPLE
NON-SOLDER MASK DEFINED
SCALE: 5X
14
SYMM
8
MAX.002
[0.05]
ALL AROUND
(R.002 ) TYP
[0.05]
(.063)
[1.6]
DETAIL A
SCALE: 15X
SOLDER MASK
OPENING
METAL
www.ti.com
METAL
SOLDER MASK
OPENING
( .063)
[1.6]
.002 MAX
[0.05]
ALL AROUND
DETAIL B
13X, SCALE: 15X
4214771/A 05/2017
Page 30
Page 31
Page 32
Page 33
Page 34
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2022, Texas Instruments Incorporated
Loading...