Page 1
SN54GTL16622A, SN74GTL16622A
18-BIT LVTTL-TO-GTL/GTL+ BUS TRANSCEIVERS
SCBS673D – AUGUST 1996 – REVISED DECEMBER 1999
D
Members of the Texas Instruments
Widebus
D
D-Type Flip-Flops With Qualified Storage
Family
Enable
D
Translate Between GTL/GTL+ Signal Levels
and LVTTL Logic Levels
D
Support Mixed-Mode (3.3 V and 5 V) Signal
Operation on A-Port and Control Inputs
D
I
Supports Partial-Power-Down Mode
off
Operation
D
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors on A Port
D
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
D
Latch-Up Performance Exceeds 250 mA Per
JESD 17
D
Distributed VCC and GND-Pin Configuration
Minimizes High-Speed Noise
D
Package Options Include Plastic Thin
Shrink Small-Outline (DGG) and Ceramic
Quad Flat (HV) Packages
description
The ’GTL16622A devices are 18-bit
registered bus transceivers that provide
LVTTL-to-GTL/GTL+ and GTL/GTL+-to-LVTTL
signal-level translation. They are partitioned as
two separate 9-bit transceivers with individual
clock-enable controls and contain D-type
flip-flops for temporary storage of data flowing in
either direction. The devices provide an interface
between cards operating at LVTTL logic levels
and a backplane operating at GTL/GTL+ signal
levels. Higher speed operation is a direct result of
the reduced output swing (<1 V), reduced input
threshold levels, and output edge control
(OEC).
SN74GTL16622A . . . DGG PACKAGE
OEAB
OEBA
1A1
GND
1A2
1A3
GND
V
CC
1A4
GND
1A5
1A6
GND
1A7
1A8
GND
1A9
2A1
GND
2A2
2A3
GND
2A4
2A5
GND
2A6
V
CC
GND
2A7
2A8
GND
2A9
(TOP VIEW)
1
64
2
63
3
62
4
61
5
60
6
59
7
58
8
57
9
56
10
55
11
54
12
53
13
52
14
51
15
50
16
49
17
48
18
47
19
46
20
45
21
44
22
43
23
42
24
41
25
40
26
39
27
38
28
37
29
36
30
35
31
34
32
33
CLKAB
1CEAB
1CEBA
1B1
GND
1B2
1B3
V
CC
1B4
1B5
1B6
GND
1B7
1B8
GND
1B9
2B1
GND
2B2
2B3
GND
2B4
2B5
2B6
V
REF
2B7
2B8
GND
2B9
2CEBA
2CEAB
CLKBA
The user has the flexibility of using this device at either GTL (V
higher noise margin GTL+ (V
= 1.5 V and V
TT
= 1 V) signal levels. GTL+ is the T exas Instruments derivative
REF
= 1.2 V and V
TT
= 0.8 V) or the preferred
REF
of the Gunning transceiver logic (GTL) JEDEC standard JESD 8-3. The B port normally operates at GTL or
GTL+ signal levels, while the A-port and control inputs are compatible with LVTTL logic levels and are 5-V
tolerant. V
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
OEC and Widebus are trademarks of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
is the reference input voltage for the B port.
REF
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1999, Texas Instruments Incorporated
1
Page 2
SN54GTL16622A, SN74GTL16622A
18-BIT LVTTL-TO-GTL/GTL+ BUS TRANSCEIVERS
SCBS673D – AUGUST 1996 – REVISED DECEMBER 1999
description (continued)
Data flow in each direction is controlled by the output-enable (OEAB and OEBA) and clock (CLKAB and CLKBA)
inputs. The clock-enable (CEAB and CEBA) inputs are designed to control each 9-bit transceiver independently ,
which makes the device more versatile.
For A-to-B data flow, the device operates on the low-to-high transition of CLKAB if CEAB is low. When OEAB
is low, the outputs are active. When OEAB is high, the outputs are in the high-impedance state. Data flow for
B to A is similar to that of A to B, but uses OEBA, CLKBA, and CEBA.
These devices are fully specified for partial-power-down applications using I
. The I
off
circuitry disables the
off
outputs, preventing damaging current backflow through the device when it is powered down.
Active bus-hold circuitry holds unused or undriven L VTTL inputs at a valid logic state. Use of pullup or pulldown
resistors with the bus-hold circuitry is not recommended.
T o ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54GTL16622A is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74GTL16622A is characterized for operation from –40°C to 85°C.
GND
1A5
1A6
GND
1A7
1A8
GND
1A9
NC
2A1
GND
2A2
2A3
GND
2A4
2A5
GND
SN54GTL16622A . . . HV PACKAGE
CC
1A4
GND
1A3
V
9876543216867666564636261
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
1A2
GND
(TOP VIEW)
NC
OEAB
1A1
CLKAB
1CEAB
1CEBA
1B1
GND
1B2
1B3
CC
V
1B4
60
1B5
59
1B6
58
GND
57
1B7
56
1B8
55
GND
54
1B9
53
NC
52
2B1
51
GND
50
2B2
49
2B3
48
GND
47
2B4
46
2B5
45
2B6
44
CC
2A6
NC – No internal connection
2
2A7
GND
2A8
GND
V
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2A9
NC
OEBA
2CEAB
CLKBA
2B9
2CEBA
GND
2B8
2B7
REF
V
Page 3
MODE
Latched storage of A data
Clocked storage of A data
SN54GTL16622A, SN74GTL16622A
18-BIT LVTTL-TO-GTL/GTL+ BUS TRANSCEIVERS
SCBS673D – AUGUST 1996 – REVISED DECEMBER 1999
FUNCTION TABLE
INPUTS
CEAB OEAB CLKAB A
X H X X Z Isolation
H L X X B
X L H or L X B
L L ↑ L L
L L ↑ H H
†
A-to-B data flow is shown. B-to-A data flow is similar, but uses OEBA, CLKBA,
and CEBA
‡
Output level before the indicated steady-state input conditions are established
.
OUTPUT
†
B
‡
0
‡
0
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
Page 4
SN54GTL16622A, SN74GTL16622A
18-BIT LVTTL-TO-GTL/GTL+ BUS TRANSCEIVERS
SCBS673D – AUGUST 1996 – REVISED DECEMBER 1999
logic diagram (positive logic)
V
REF
OEAB
1CEAB
CLKAB
CLKBA
1CEBA
OEBA
1A1
40
1
63
64
33
62
32
2
CLK
CE
1D
CE
1D
CLK
61
1B1
2A1
34
35
17
2CEAB
2CEBA
Pin numbers shown are for the DGG package.
CLK
To Eight Other Channels
CE
1D
To Eight Other Channels
CE
1D
CLK
48
2B1
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Page 5
UNIT
V
V
V
Suppl
oltage
V
VIInput voltage
V
V
g
V
V
V
I
mA
SN54GTL16622A, SN74GTL16622A
18-BIT LVTTL-TO-GTL/GTL+ BUS TRANSCEIVERS
SCBS673D – AUGUST 1996 – REVISED DECEMBER 1999
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, VCC –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1): A-port and control inputs –0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . .
B port and V
Voltage range applied to any output in the high or power-off state, V
–0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
REF
O
(see Note 1): A port –0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B port –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current into any output in the low state, IO: A port 48 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B port 100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current into any A-port output in the high state, I
(see Note 2) 48 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
Continuous current through each VCC or GND ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
Output clamp current, I
(V
< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IK
I
(V
OK
< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
Package thermal impedance, θJA (see Note 3) 55°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This current flows only when the output is in the high state and VO > VCC.
3. The package thermal impedance is calculated in accordance with JESD 51.
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
recommended operating conditions (see Notes 4 through 6)
SN54GTL16622A SN74GTL16622A
MIN NOM MAX MIN NOM MAX
V
I
IK
I
OH
OL
T
NOTES: 4. All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Supply voltage 3.15 3.3 3.45 3.15 3.3 3.45 V
CC
Termination
TT
voltage
pp
REF
IH
IL
A
y v
p
High-level
input voltage
Low-level
input voltage
Input clamp current –18 –18 mA
High-level
output current
Low-level
output current
Operating free-air temperature –55 125 –40 85 °C
Implications of Slow or Floating CMOS Inputs
5. Normal connection sequence is GND first and VCC = 3.3 V, I/O, control inputs, VTT and V
6. VTT and RTT can be adjusted to accommodate backplane impedances as long as they do not exceed the DC absolute IOL ratings.
Similarly , V
GTL 1.14 1.2 1.26 1.14 1.2 1.26
GTL+
GTL 0.74 0.8 0.87 0.74 0.8 0.87
GTL+ 0.87 1 1.1 0.87 1 1.1
B port V
Except B port 5.5 5.5
B port V
Except B port
B port V
Except B port
A port –24 –24 mA
A port 24 24
B port
can be adjusted to optimize noise margins, but normally is 2/3 VTT.
REF
1.35 1.5 1.65 1.35 1.5 1.65
TT
+50 mV V
REF
2 2
–50 mV V
REF
0.8 0.8
50 50
, literature number SCBA004.
REF
+50 mV
(any order) last.
REF
V
REF
TT
–50 mV
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
Page 6
SN54GTL16622A, SN74GTL16622A
PARAMETER
TEST CONDITIONS
UNIT
V
V
V
3.15 V
B port
V
V
V
V
()
V
CC
C
V
0
pF
18-BIT LVTTL-TO-GTL/GTL+ BUS TRANSCEIVERS
SCBS673D – AUGUST 1996 – REVISED DECEMBER 1999
electrical characteristics over recommended operating free-air temperature range for GTL/GTL+
(unless otherwise noted)
SN54GTL16622A SN74GTL16622A
MIN TYP†MAX MIN TYP†MAX
V
IK
V
V
I
I
I
off
I
I(hold)
I
OZ
I
OZH
I
CC
∆I
C
†
All typical values are at VCC = 3.3 V, TA = 25°C.
‡
This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.
§
For I/O ports, the parameter IOZ includes the input leakage current.
¶
This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
A port
OH
A port
OL
p
B port
A-port and
control inputs
A port
§
A port VCC = 3.45 V, VO = VCC or GND ±10 ±10 µA
B port VCC = 3.45 V, VO = 1.5 V 10 10 µA
A or B port
¶
CC
Control inputs VI = 3.15 V or 0 2.5 3 2.5 3 pF
i
A port
io
B port
VCC = 3.15 V, II = –18 mA –1.2 –1.2 V
VCC = 3.15 V to 3.45 V, IOH = –100 µA VCC–0.2 VCC–0.2
= 3.15
CC
VCC = 3.15 V to 3.45 V, IOL = 100 µA 0.2 0.2
=
CC
VCC = 3.15 V to 3.45 V, IOL = 100 µA 0.2 0.2
VCC = 3.15 V
VCC = 3.45 V VI = VTT or GND ±5 ±5
= 3.45
CC
VCC = 0, VI or VO = 0 to 5.5 V 100 100 µA
= 3.15
CC
VCC = 3.45 V‡, VI = 0.8 V to 2 V ±500 ±500
=
= 3.45 V,
IO = 0,
VI = VCC or GND
VCC = 3.45 V,
A-port or control inputs at VCC or GND,
One input at VCC – 0.6 V
= 3.15 V or
O
IOH = –12 mA 2.4 2.4
IOH = –24 mA 2 2
IOL = 12 mA 0.4 0.4
IOL = 24 mA 0.5 0.5
IOL = 10 mA 0.2 0.2
IOL = 40 mA 0.4 0.4
IOL = 50 mA 0.55 0.55
VI = VCC or GND ±5 ±5
VI = 5.5 V or GND ±20 ±20
VI = 0.8 V 75 75
VI = 2 V –75 –75
Outputs high 60 60
Outputs low 60 60
Outputs disabled 60 60
500 500 µA
6 8.5 6 8
7 9.5 6.5 8.5
µA
µA
mA
p
V
V
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Page 7
UNIT
tsuSetup time
ns
thHold time
ns
PARAMETER
UNIT
CLKAB
B
ns
OEAB
B
ns
CLKBA
A
ns
OEBA
A
ns
SN54GTL16622A, SN74GTL16622A
18-BIT LVTTL-TO-GTL/GTL+ BUS TRANSCEIVERS
SCBS673D – AUGUST 1996 – REVISED DECEMBER 1999
timing requirements over recommended ranges of supply voltage and operating free-air
temperature for GTL (unless otherwise noted)
SN54GTL16622A SN74GTL16622A
MIN MAX MIN MAX
f
clock
t
w
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature for GTL (see Figure 1)
†
All typical values are at VCC = 3.3 V, TA = 25°C.
Clock frequency 200 200 MHz
Pulse duration, CLK high or low 2.5 2.5 ns
p
FROM TO
(INPUT) (OUTPUT)
f
max
t
PLH
t
PHL
t
dis
t
en
Slew rate Both transitions (B port) 0.5 0.5 V/ns
t
r
t
f
t
PLH
t
PHL
t
en
t
dis
Transition time, B outputs (0.6 V to 1 V) 0.5 2.3 0.6 2.2 ns
Transition time, B outputs (1 V to 0.6 V) 0.3 1.7 0.4 1.5 ns
Data before CLK↑ 2.5 2.1
CE before CLK↑ 3.5 3.3
Data after CLK↑ 0.3 0.3
CE after CLK↑ 0.3 0
SN54GTL16622A SN74GTL16622A
MIN TYP†MAX MIN TYP†MAX
200 200 MHz
2.4 5.7 2.5 5.5
2.1 5.7 2.2 5.5
1.6 5 1.7 4.8
2.1 5.5 2.2 5.2
1.9 5.5 2.1 5.3
1.8 5.3 2.1 5
1.6 5.3 1.7 5
2 5.8 2.3 5.5
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7
Page 8
SN54GTL16622A, SN74GTL16622A
UNIT
tsuSetup time
ns
thHold time
ns
PARAMETER
UNIT
CLKAB
B
ns
OEAB
B
ns
CLKBA
A
ns
OEBA
A
ns
18-BIT LVTTL-TO-GTL/GTL+ BUS TRANSCEIVERS
SCBS673D – AUGUST 1996 – REVISED DECEMBER 1999
timing requirements over recommended ranges of supply voltage and operating free-air
temperature for GTL+ (unless otherwise noted)
SN54GTL16622A SN74GTL16622A
MIN MAX MIN MAX
f
clock
t
w
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature for GTL+ (see Figure 1)
†
All typical values are at VCC = 3.3 V, TA = 25°C.
Clock frequency 200 200 MHz
Pulse duration, CLK high or low 2.5 2.5 ns
p
FROM TO
(INPUT) (OUTPUT)
f
max
t
PLH
t
PHL
t
PLH
t
PHL
Slew rate Both transitions (B port) 0.5 0.5 V/ns
t
r
t
f
t
PLH
t
PHL
t
en
t
dis
Transition time, B outputs (0.6 V to 1.3 V) 0.9 2.8 1 1.6 2.7 ns
Transition time, B outputs (1.3 V to 0.6 V) 0.4 3.7 0.5 1.1 3.2 ns
Data before CLK↑ 2.5 2.4
CE before CLK↑ 3.4 3.2
Data after CLK↑ 0.3 0.2
CE after CLK↑ 0.1 0
SN54GTL16622A SN74GTL16622A
MIN TYP†MAX MIN TYP†MAX
200 200 MHz
2.5 5.8 2.6 4 5.6
2.2 6.1 2.3 4 5.7
2.3 5.5 2.4 3.8 5.2
1.7 5.3 1.8 3.4 5
1.9 5.5 2 3.8 5.3
1.8 5.3 1.9 3.6 5
1.8 5.3 1.9 3.6 5
2 5.8 2.1 4 5.5
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Page 9
SN54GTL16622A, SN74GTL16622A
18-BIT LVTTL-TO-GTL/GTL+ BUS TRANSCEIVERS
SCBS673D – AUGUST 1996 – REVISED DECEMBER 1999
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT FOR A OUTPUTS
Input
Input
(see Note B)
Output
Input
(see Note B)
Output
500 Ω
500 Ω
t
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
1.5 V 1.5 V
t
PLH
V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
(CLKAB to B port)
1.5 V 1.5 V
t
PLH
1.5 V 1.5 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
(CLKBA to A port)
w
REF
S1
6 V
GND
1.5 V
Open
V
t
PHL
REF
t
PHL
3 V
0 V
3 V
0 V
V
V
3 V
0 V
V
V
OH
OL
OH
OL
TEST
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
(see Note B)
Waveform 1
(see Note C)
Waveform 2
(see Note C)
Timing
Input
Data Input
A Port
Data Input
B Port
Output
Control
Output
S1 at 6 V
Output
S1 at GND
S1
Open
6 V
GND
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
PZL
t
PZH
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
From Output
Under Test
LOAD CIRCUIT FOR B OUTPUTS
t
su
1.5 V
V
REF
1.5 V 1.5 V
1.5 V
1.5 V
(OEBA
to A port)
CL = 30 pF
(see Note A)
1.5 V
t
h
VOL + 0.3 V
VOH – 0.3 V
V
TT
1.5 V
V
REF
t
PLZ
t
PHZ
25 Ω
Test
Point
3 V
0 V
3 V
0 V
V
TT
0 V
3 V
0 V
3 V
V
OL
V
OH
≈0 V
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
9
Page 10
IMPORTANT NOTICE
T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICA TIONS USING SEMICONDUCT OR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICA TIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERST OOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1999, Texas Instruments Incorporated
Loading...