Page 1
D
Compatible With IEEE Std 1 194.1-1991
(BTL)
D
TTL A Port, Backplane Transceiver Logic
(BTL) B
D
Open-Collector B-Port Outputs Sink
Port
100 mA
D
BIAS VCC Pin Minimizes Signal Distortion
During Live Insertion/Withdrawal
8-BIT TTL/BTL REGISTERED TRANSCEIVER
D
D
D
D
RC PACKAGE
(TOP VIEW)
SN74FB2033K
SCBS472E – MAY 1994 – REVISED JUNE 1997
High-Impedance State During Power Up
and Power Down
B-Port Biasing Network Preconditions the
Connector and PC Trace to the BTL
High-Level Voltage
TTL-Input Structures Incorporate Active
Clamping Networks to Aid in Line
Termination
Packaged in Plastic Quad Flatpack
description
GND
AO2
AI3
AO3
AI4
AO4
LOOPBACK
AI5
AO5
AI6
AO6
AI7
GND
CC
CC
AO1
AI8
AI1
AO8
GND
V
V
GND
CC
CLKAB/LEAB
IMODE1
IMODE0
BG V
CC
V
OMODE0
OMODE1
CLKBA/LEBA
OEA
OEB
AI2
52 51 50 49 48 47 46 45 44 43 42 41 40
1
2
3
4
5
6
7
8
9
10
11
12
13
14 15 16 17 18 19 20 21 22 23 24 25 26
AO7
CC
BIAS V
BG GND
B1
39
38
37
36
35
34
33
32
31
30
29
28
27
B8
OEB
GND
GND
B2
GND
B3
GND
B4
GND
B5
GND
B6
GND
B7
GND
The SN74FB2033K is an 8-bit transceiver featuring a split input (AI) and output (AO) bus on the TTL-level A port.
The common I/O, open-collector B port operates at backplane transceiver logic (BTL) signal levels. The
SN74FB2033K is specifically designed to be compatible with IEEE Std 1194.1-1991.
The logic element for data flow in each direction is configured by two mode inputs (IMODE1 and IMODE0 for
B-to-A, OMODE1 and OMODE0 for A-to-B) as a buffer , a D-type flip-flop, or a D-type latch. When configured
in the buffer mode, the inverted input data appears at the output port. In the flip-flop mode, data is stored on
the rising edge of the appropriate clock input (CLKAB/LEAB or CLKBA/LEBA). In the latch mode, the clock
inputs serve as active-high transparent latch enables.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1997, Texas Instruments Incorporated
1
Page 2
SN74FB2033K
FUNCTION/MODE
Isolation
B
B
flip-fl
B
AI to AO, buffer mode
AI to AO, flip-flop mode
AI to AO, latch mode
8-BIT TTL/BTL REGISTERED TRANSCEIVER
SCBS472E – MAY 1994 – REVISED JUNE 1997
description (continued)
Data flow in the B-to-A direction, regardless of the logic element selected, is further controlled by the
LOOPBACK input. When LOOPBACK is low, B-port data is the B-to-A input. When LOOPBACK is high, the
output of the selected A-to-B logic element (before inversion) is the B-to-A input.
The AO port-enable/-disable control is provided by OEA. When OEA is low or when V
is less than 2.5 V , the
CC
AO port is in the high-impedance state. When OEA is high, the AO port is active (high or low logic levels).
port is controlled by OEB and OEB. If OEB is low, or OEB is high, or when VCC is less than 2.5 V , the B port
The B
is inactive. If OEB is high and OEB
BG V
and BG GND are the bias-generator reference inputs.
CC
is low, the B port is active.
The A-to-B and B-to-A logic elements are active, regardless of the state of their associated outputs. The logic
elements can enter new data (in flip-flop and latch modes) or retain previously stored data while the associated
outputs are in the high-impedance (AO port) or inactive (B port) states.
Output clamps are provided on the BTL outputs to reduce switching noise. One clamp reduces inductive ringing
effects on VOH during a low-to-high transition. The other clamps out ringing below the BTL VOL voltage of 0.75 V .
Both of these clamps are active only during ac switching and do not affect the BTL outputs during steady-state
conditions.
BIAS VCC establishes a voltage between 1.62 V and 2.1 V on the BTL outputs when VCC is not connected.
The SN74FB2033K is characterized for operation from 0°C to 70°C.
Function Tables
FUNCTION
INPUTS
OEA OEB OEB OMODE1 OMODE0 IMODE1 IMODE0 LOOPBACK
L L X X X X X X
L XH X X X X X
X H L L L X X X AI to B, buffer mode
X H L L H X X X AI to B, flip-flop mode
X H L H X X X X AI to B, latch mode
H L X X X L L L
H XH X X L L L
H L X X X L H L
H XH X X L H L
H L X X X H X L
H XH X X H X L
H L X X X L L H
H XH X X L L H
H L X X X L H H
H XH X X L H H
H L X X X H X H
H XH X X H X H
H H L X X X X L AI to B, B to AO
to AO, buffer mode
to AO,
to AO, latch mode
op mode
p
p
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Page 3
OUTPUT
OUTPUT
SN74FB2033K
8-BIT TTL/BTL REGISTERED TRANSCEIVER
SCBS472E – MAY 1994 – REVISED JUNE 1997
Function Tables (Continued)
ENABLE/DISABLE
INPUTS
OEA OEB OEB AO B
L X X Hi Z
H X X Active
X LL Inactive (H)
X LH Inactive (H)
X HL Active
X H H Inactive (H)
BUFFER
INPUT
L H
H L
LATCH
INPUTS
CLK/LE DATA
H L H
H HL
L X Q
OUTPUTS
OUTPUT
0
LOOPBACK
LOOPBACK
L B port
H Point P
†
Q is the input to the B-to-A
logic element.
‡
P is the output of the A-to-B
logic element (see functional
block diagram).
SELECT
INPUTS
MODE1 MODE0
L L Buffer
L H Flip-flop
H X Latch
INPUTS
CLK/LE DATA
L X Q
↑ LH
↑ H L
SELECTED-LOGIC
ELEMENT
FLIP-FLOP
†
Q
‡
0
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
Page 4
SN74FB2033K
8-BIT TTL/BTL REGISTERED TRANSCEIVER
SCBS472E – MAY 1994 – REVISED JUNE 1997
functional block diagram
23
OEB
24
OEB
AI1
21
20
47
Transceiver
1D
C1
50
1D
C1
OMODE1
OMODE0
CLKAB/LEAB
40
B1
P
IMODE1
IMODE0
CLKBA/LEBA
AO1
OEA
LOOPBACK
46
45
19
51
43
7
One of Eight Channels
Transceiver
1D
C1
Q
1D
C1
One of Eight Channels
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Page 5
VIHHigh-level input voltage
V
VILLow-level input voltage
V
IOLLow-level output current
mA
SN74FB2033K
8-BIT TTL/BTL REGISTERED TRANSCEIVER
SCBS472E – MAY 1994 – REVISED JUNE 1997
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
Voltage range applied to any B output in the disabled or power-off state,VO –0.5 V to 3.5 V. . . . . . . . . . . . . .
Voltage range applied to any output in the high state, VO: A port –0.5 V to V
Input voltage range, VI: Except B port –1.2 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
Current applied to any single output in the low state, IO: A port 48 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 1): RC package 79°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The package thermal impedance is calculated in accordance with JESD 51.
–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
. . . . . . . . . . . . . . . . . . . . . . . .
B port –1.2 V to 3.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
: Except B port –40 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IK
B port –18 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B port 200 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
recommended operating conditions (see Note 2)
MIN NOM MAX UNIT
VCC, BG V
BIAS V
CC
I
OH
∆t/∆v Input transition rise or fall rate Except B port 10 ns/V
T
A
NOTE 2: Unused pins (input or I/O) must be held high or low to prevent them from floating.
Supply voltage 4.75 5 5.25 V
CC
Supply voltage 4.5 5 5.5 V
p
p
High-level output current AO port –3 mA
p
Operating free-air temperature 0 70 °C
B port 1.62 2.3
Except B port 2
B port 0.75 1.47
Except B port 0.8
AO port 24
B port 100
†
CC
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
Page 6
SN74FB2033K
V
V
V
V
AO port
V
V
V
V
B
V
4.75 V
I
A
I
A
C
§
pF
8-BIT TTL/BTL REGISTERED TRANSCEIVER
SCBS472E – MAY 1994 – REVISED JUNE 1997
electrical characteristics over recommended operating free-air temperature range
PARAMETER TEST CONDITIONS MIN TYP
IK
V
OH
OL
I
I
IH
IL
I
OH
I
OZH
I
OZL
I
OZPU
I
OZPD
I
OS
I
CC
C
i
C
o
io
†
All typical values are at VCC = 5 V, TA = 25°C
‡
For I/O ports, the parameters IIH and IIL include the off-state output current.
§
This parameter is warranted but not production tested.
¶
Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.
B port VCC = 4.75 V, II = –18 mA –1.2
Except B port VCC = 4.75 V, II = –40 mA –0.5
VCC = 4.75 V to 5.25 V, IOH = –10 µA VCC–1.1
AO port
p
port
Except B port VCC = 0, VI = 5.25 V 100 µA
Except B port VCC = 5.25 V, VI = 2.7 V 50
‡
B port
Except B port VCC = 5.25 V, VI = 0.5 V –50
‡
B port
B port VCC = 0 to 5.25 V, VO = 2.1 V 100 µA
AO port VCC = 2.1 V to 5.25 V, VO = 2.7 V 50 µA
AO port VCC = 2.1 V to 5.25 V, VO = 0.5 V –50 µA
§
A port VCC = 0 to 2.1 V, VO = 0.5 V to 2.7 V 50 µA
§
A port VCC = 2.1 V to 0, VO = 0.5 V to 2.7 V –50 µA
¶
AO port VCC = 5.25 V, VO = 0 –40 –80 –150 mA
All outputs on VCC = 5.25 V, IO = 0 45 70 mA
AI port and control inputs VI = 0.5 V or 2.5 V 5 pF
AO port VO = 0.5 V or 2.5 V 5 pF
B port
per IEEE Std 1194.1-1991
= 4.75
CC
= 4.75
CC
=
CC
VCC = 0 to 5.25 V, VI = 2.1 V 100
VCC = 5.25 V, VI = 0.75 V –100
VCC = 0 to 4.75 V 6
VCC = 4.75 V to 5.25 V 6
IOH = –3 mA 2.5 2.85 3.4
IOH = –32 mA 2
IOL = 20 mA 0.33 0.5
IOL = 55 mA 0.8
IOL = 100 mA 0.75 1.1
IOL = 4 mA 0.5
†
MAX UNIT
V
µ
µ
p
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Page 7
I
(BIAS VCC)
SN74FB2033K
8-BIT TTL/BTL REGISTERED TRANSCEIVER
SCBS472E – MAY 1994 – REVISED JUNE 1997
live-insertion characteristics over recommended operating free-air temperature range (see Note 3)
PARAMETER TEST CONDITIONS MIN MAX UNIT
CC
V
I
O
NOTE 3: Power-up sequence is as follows: GND, BIAS VCC, VCC.
B port VCC = 0, BIAS VCC = 5 V 1.62 2.1 V
O
B port
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 2)
f
clock
t
w
t
su
t
h
Clock frequency 0 150 0 150 MHz
Pulse duration, CLKAB/LEAB or CLKBA/LEBA 3.3 3.3 ns
Setup time, data before CLKAB/LEAB or CLKBA/LEBA↑ 2.7 2.7 ns
Hold time, data after CLKAB/LEAB or CLKBA/LEBA↑ 0.7 0.7 ns
VCC = 0 to 4.75 V VB = 0 to 2 V, BIAS VCC = 4.5 V to 5.5 V 1.2 mA
VCC = 4.75 V to 5.25 V VB = 0 to 2 V, BIAS VCC = 4.5 V to 5.5 V 10 µA
VCC = 0, VB = 1 V, VI (BIAS VCC) = 4.75 V to 5.25 V –1
VCC = 0 to 5.25 V, OEB = 0 to 0.8 V 100
VCC = 0 to 2.2 V, OEB = 0 to 5 V 100
VCC = 5 V,
TA = 25°C
MIN MAX
MIN MAX UNIT
µA
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7
Page 8
SN74FB2033K
(INPUT)
(OUTPUT)
AI (through mode)
B
ns
B (th
)
AO
ns
AI (transparent)
B
ns
B (
)
AO
ns
OEB
B
ns
OEB
B
ns
OEA
AO
ns
OEA
AO
ns
CLKAB/LEAB
B
ns
CLKBA/LEBA
AO
ns
OMODE
B
ns
IMODE
AO
ns
LOOPBACK
AO
ns
AI
AO
ns
ns
ns
8-BIT TTL/BTL REGISTERED TRANSCEIVER
SCBS472E – MAY 1994 – REVISED JUNE 1997
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 2)
PARAMETER
f
max
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
trRise time, 1.3 V to 1.8 V, B port 1.8 2.5 3.8 1.7 4
tfFall time, 1.8 V to 1.3 V, B port 1.7 2.5 3.8 1.5 4
trRise time, 10% to 90%, AO 2.5 3.4 4.8 2 5
tfFall time, 90% to 10%, AO 1.5 2.5 3.8 1 5
B-port input pulse rejection
FROM
rough mode
p
transparent
TO
VCC = 5 V,
TA = 25°C
MIN TYP MAX
150 150 MHz
2.8 5.1 6.8 2.8 8.1
2.5 4.2 5.7 2.5 6.1
3.1 4.3 5.1 2.2 6.6
3.1 4.2 5.1 2.6 6
2.8 5.1 6.8 2.8 8.1
2.6 4.2 5.7 2.6 6.1
2.2 4.3 6 2.2 6.6
2.5 4.2 5.6 2.5 6
2.7 5.1 6.8 2.7 8.3
2.4 4.2 5.7 2.4 6.1
2.5 4.8 6.4 2.5 7.7
2.5 4.3 5.9 2.5 6.4
1.6 3.6 5.1 1.6 5.6
2.3 4.3 5.7 2.3 6
1.7 4 5.5 1.7 5.9
1.2 2.9 4.4 1.2 4.7
5.2 6.5 7.8 3.7 9.9
3.8 5.4 7.1 3.4 7.7
1.7 3.8 5.5 1.7 5.9
1.8 3.6 5.1 1.8 5.5
2.9 6.6 8.4 2.9 10
3 5.7 7.5 3 8.3
1.4 4.1 5.8 1.4 6.4
1.9 4.2 5.7 1.9 5.9
2 5.2 7.3 2 8.2
2.6 4.8 6.3 2.6 6.4
1.7 3.9 5.6 1.7 6.1
2.2 4.3 5.7 2.2 5.9
MIN MAX UNIT
1 ns
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Page 9
output-voltage characteristics
PARAMETER TEST CONDITIONS MIN MAX UNIT
†
V
OHP
V
OHV
V
OLV
†
This parameter is warranted but not production tested.
Peak output voltage during turnoff of 100 mA into 40 nH B port See Figure 1 3 V
†
Minimum output voltage during turnoff of 100 mA into 40 nH B port See Figure 1 1.62 V
Minimum output voltage during high-to-low switch B port IOL = –50 mA 0.3 V
PARAMETER MEASUREMENT INFORMATION
SN74FB2033K
8-BIT TTL/BTL REGISTERED TRANSCEIVER
SCBS472E – MAY 1994 – REVISED JUNE 1997
2.1 V
From Output
Under Test
40 nH
Figure 1. Load Circuit for V
OHP
9 Ω
30 pF
and V
OHV
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
9
Page 10
SN74FB2033K
8-BIT TTL/BTL REGISTERED TRANSCEIVER
SCBS472E – MAY 1994 – REVISED JUNE 1997
PARAMETER MEASUREMENT INFORMATION
2.1 V
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT FOR A OUTPUTS
Timing Input
Data Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Input 1.5 V 1.5 V
Output
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES (A TO B)
Input
500 Ω
500 Ω
t
su
1.5 V 1.5 V
t
PHL
1.5 V
t
h
7 V
S1
1.55 V1.55 V
1.55 V1.55 V
t
PLH
Open
3 V
0 V
3 V
0 V
3 V
0 V
V
V
2.1 V
1 V
From Output
Under Test
CL = 30 pF
(see Note A)
LOAD CIRCUIT FOR B OUTPUTS
Output
Control
Output
Waveform 1
S1 at 7 V
(see Note B)
OH
OL
Output
Waveform 2
S1 at Open
(see Note B)
ENABLE AND DISABLE TIMES (A PORT)
9 Ω
Test
Point
1.5 V 1.5 VInput
VOLTAGE WAVEFORMS
PULSE DURATION
1.5 V 1.5 V
t
PZL
1.5 V
t
PZH
1.5 V
VOLTAGE WAVEFORMS
TEST S1
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
t
w
Open
7 V
Open
t
PLZ
VOL + 0.3 V
t
PHZ
VOH – 0.3 V
3 V
0 V
3 V
0 V
3.5 V
V
OL
V
OH
≈ 0 V
t
PHL
Output
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES (B TO A)
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: TTL inputs: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns,
tf≤ 2.5 ns; BTL inputs: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
1.5 V 1.5 V
Figure 2. Load Circuit and Voltage Waveforms
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
t
PLH
V
OHP
V
OH
V
OL
VOLTAGE WAVEFORMS
V
OHV
2.1 V
V
1 V
OLV
Page 11
IMPORTANT NOTICE
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any product or service without notice, and advise customers to obtain the latest version of relevant information
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pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
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Copyright 1998, Texas Instruments Incorporated
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