Page 1
D
Compatible With IEEE Std 1 194.1-1991
(BTL)
D
TTL A Port, Backplane Transceiver Logic
(BTL) B Port
D
Open-Collector B-Port Outputs Sink
100 mA
D
Isolated Logic-Ground and Bus-Ground
Pins Reduce Noise
D
High-Impedance State During Power Up
and Power Down
SN74FB2031
9-BIT TTL/BTL ADDRESS/DATA TRANSCEIVER
SCBS176K – NOVEMBER 1991 – REVISED SEPTEMBER 1999
D
BIAS VCC Minimizes Signal Distortion
During Live Insertion or Withdrawal
D
B-Port Biasing Network Preconditions the
Connector and PC Trace to the BTL
High-Level Voltage
D
TTL-Input Structures Incorporate Active
Clamping to Aid in Line Termination
D
Packaged in Plastic Quad Flatpack
RC PACKAGE
(TOP VIEW)
CC
GND
A3
GND
A4
GND
A5
GND
A6
GND
A7
GND
A8
GND
GND
A1
LCB
SEL1
CC
V
CC
LCA
BG V
OEA
BIAS V
BG GND
OEB
SEL0
A2
52 51 50 49 48 47 46 45 44 43 42 41 40
1
2
3
4
5
6
7
8
9
10
11
12
13
14 15 16 17 18 19 20 21 22 23 24 25 26
A9
OEB
TDO
TCK
TDI
V
V
CC
CC
TMS
B9
GND
GND
B1
39
38
37
36
35
34
33
32
31
30
29
28
27
B8
GND
B2
GND
B3
GND
B4
GND
B5
GND
B6
GND
B7
GND
description
The SN74FB2031 device is a 9-bit transceiver designed to translate signals between TTL and backplane
transceiver logic (BTL) environments. It is specifically designed to be compatible with IEEE Std 1 194.1-1991.
The B port operates at BTL-signal levels. The open-collector B ports are specified to sink 100 mA. Two output
enables (OEB and OEB) are provided for the B outputs. When OEB is low, OEB is high, or VCC is less than 2.1 V ,
the B
port is turned off.
The A port operates at TTL signal levels. The A outputs reflect the inverse of the data at the B
port when the
A-port output enable (OEA) is high. When OEA is low or VCC is less than 2.1 V, the A outputs are in the
high-impedance state.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1999, Texas Instruments Incorporated
1
Page 2
SN74FB2031
FUNCTION
B d
Isolation
9-BIT TTL/BTL ADDRESS/DATA TRANSCEIVER
SCBS176K – NOVEMBER 1991 – REVISED SEPTEMBER 1999
description (continued)
Pins are allocated for the 4-wire IEEE Std 1149.1 (JT AG) test bus. TMS and TCK are not connected and TDI
is shorted to TDO.
BIAS VCC establishes a voltage between 1.62 V and 2.1 V on the BTL outputs when VCC is not connected.
BG VCC and BG GND are the supply inputs for the bias generator.
The SN74FB2031 is characterized for operation from 0°C to 70°C.
Function Tables
TRANSCEIVER
INPUTS
OEA OEB OEB
L H L A data to B bus
H L X
H XH
H H L A data to B bus, B data to A bus
L L X
L X H
ata to A bus
STORAGE MODE
SELECT
MUX
A→B
RESULT
MUX
B→A
LCA, LCB
0 Transparent
1 Latches latched
↑ Flip-flops triggered
SEL0
SEL1
0 0 Latch Latch
0 1 Through Through
1 0 Flip-flop Flip-flop
1 1 Flip-flop Latch
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Page 3
functional block diagram
18
LCA
SN74FB2031
9-BIT TTL/BTL ADDRESS/DATA TRANSCEIVER
SCBS176K – NOVEMBER 1991 – REVISED SEPTEMBER 1999
SEL0
SEL1
LCB
OEB
OEB
OEA
A1
20
15
16
46
45
47
50
1D
C1
1D
C1
MUX
MUX
C1
1D
C1
1D
40
B1
To Eight Other Channels
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI: Except B port –1.2 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B
port –1.2 V to 3.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any B output in the disabled or power-off state, VO –0.5 V to 3.5 V. . . . . . . . . . . . . .
Voltage range applied to any output in the high state, VO –0.5 V to V
Input clamp current, IIK: Except B port –40 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B port –18 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current applied to any single output in the low state, I
Package thermal impedance, θ
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The package thermal impedance is calculated in accordance with JESD 51.
(see Note 1) 44°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
: A port 48 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
B port 200 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
CC
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3
Page 4
SN74FB2031
VIHHigh-level input voltage
V
VILLow-level input voltage
V
IOLLow-level output current
mA
V
V
VOHA port
V
4.5 V
V
A port
V
4.5 V
V
V
B
V
V
I
‡
V
V
A
I
V
I
078mA
9-BIT TTL/BTL ADDRESS/DATA TRANSCEIVER
SCBS176K – NOVEMBER 1991 – REVISED SEPTEMBER 1999
recommended operating conditions (see Note 2)
MIN NOM MAX UNIT
V
CC,
BIAS VCC,
BG V
CC
I
OH
T
A
NOTE 2: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
IK
OL
I
I
‡
I
IH
IL
I
OZH
I
OZL
I
OZPU
I
OZPD
I
OH
§
I
OS
CC
C
i
C
io
†
All typical values are at VCC = 5 V, TA = 25°C.
‡
For I/O ports, the parameters IIH and IIL include the off-state output current.
§
Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.
Supply voltage 4.5 5 5.5 V
p
p
High-level output current A port –3 mA
p
Operating free-air temperature 0 70 °C
Implications of Slow or Floating CMOS Inputs
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
B port VCC = 4.5 V, II = –18 mA –1.2
Except B port VCC = 4.5 V, II = –40 mA –0.5
p
p
port
Except B port VCC = 5.5 V, VI = 5.5 V 50 µA
Except B port VCC = 5.5 V, VI = 2.7 V 50 µA
Except B port
B port
A port VCC = 2.1 V to 5.5 V, VO = 2.7 V 50 µA
A port VCC = 2.1 V to 5.5 V, VO = 0.5 V –50 µA
A port VCC = 0 to 2.1 V, VO = 0.5 V to 2.7 V 50 µA
A port VCC = 2.1 V to 0, VO = 0.5 V to 2.7 V –50 µA
B port VCC = 0 to 5.5 V, VO = 2.1 V 100 µA
A port VCC = 5.5 V, VO = 0 –30 –150 mA
A port to B port
B port to A port
VI = 0.5 V or 2.5 V 4.5 pF
A port
B port
per IEEE Std 1194.1-1991
VO = 0.5 V or 2.5 V 8.5
VCC = 0 to 5.5 V 6
, literature number SCBA004.
=
CC
=
CC
= 4.5
CC
= 5.5
CC
= 5.5 V,
CC
IOH = –1 mA
IOH = –3 mA 2.5 3.3
IOL = 20 mA
IOL = 24 mA 0.35 0.5
IOL = 80 mA 0.75 1.1
IOL = 100 mA 1.15
VI = 0.5 V –50
VI = 0.75 V –100
O
B port 1.62 2.3
Except B port 2
B port 0.75 1.47
Except B port 0.8
A port 24
B port 100
=
78
µ
pF
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Page 5
I
(BIAS VCC)
V
V
(BIAS VCC)
V
A
Clock mode
tsuSetup time
ns
Latch mode
Clock mode
thHold time
ns
Latch mode
SN74FB2031
9-BIT TTL/BTL ADDRESS/DATA TRANSCEIVER
SCBS176K – NOVEMBER 1991 – REVISED SEPTEMBER 1999
live-insertion specifications over recommended operating free-air temperature range
PARAMETER TEST CONDITIONS MIN MAX UNIT
VCC = 0 to 4.5 V
VCC = 4.5 V to 5.5 V
VCC = 0, VB = 1 V, VI (BIAS VCC) = 4.5 V to 5.5 V –1
VCC = 0 to 5.5 V, OEB = 0 to 0.8 V 100
VCC = 0 to 2.2 V, OEB = 0 to 5 V 100
= 0 to 2 V,
B
I
= 4.5 V to 5.5
V
I
CC
O
O
B port VCC = 0, VI (BIAS VCC) = 5 V 1.62 2.1 V
B port
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
MIN MAX UNIT
f
clock
t
w
Clock frequency 150 MHz
Pulse duration LCA or LCB 3.3 ns
Data before LCA↑ 1.4
p
Data before LCB↑ 2.8
Data before LCA↑ 1.1
Data before LCB↑ 2.4
Data after LCA↑ 0.6
Data after LCB↑ 0
Data after LCA↑ 0.9
Data after LCB↑ 0
450
10
µ
µA
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5
Page 6
SN74FB2031
(INPUT)
(OUTPUT)
B
ns
B
ns
LCA
B
ns
LCB
A
ns
SEL1 or SEL0
A
ns
SEL1 or SEL0
B
ns
B
A
ns
B
A
ns
OEB
OEB
B
ns
OEA
A
ns
OEA
A
ns
t
Pulse ske
ns
t
Pulse ske
ns
t
ns
9-BIT TTL/BTL ADDRESS/DATA TRANSCEIVER
SCBS176K – NOVEMBER 1991 – REVISED SEPTEMBER 1999
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
PARAMETER
f
max
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
sk(p)
sk(o)
t
B-port input pulse rejection 1 1 ns
Transition time, B outputs (1.3 V to 1.8 V) 0.6 2 2.8 0.4 2.9
Transition time, A outputs (10% to 90%) 0.5 3.5 4.7 0 5.4
w
w
FROM
A
(through mode)
A
(transparent)
B
(through mode)
B
(transparent)
or
A
B
A
B
TO
B
A
B
A
VCC = 5 V,
TA = 25°C
MIN TYP MAX
150 150 MHz
3.7 4.5 5.9 3.2 6.6
2.9 4 5.7 2.6 5.9
4.1 5 6.5 3.6 7.3
3.3 4.5 6.1 3 6.5
4.5 5.4 7 3.9 7.8
4 5.1 6.7 3.4 7.4
2.8 3.7 4.7 1.9 6
2.5 3.4 4.9 1.8 5.5
2.5 3.8 5.3 1.9 6.3
2.2 3.5 5.1 1.6 5.6
4.1 5.3 6.9 3.7 7.8
3.7 5.2 6.9 3.3 7.7
3.1 4 5.6 2.2 7.1
2.6 3.4 4.9 1.4 5.7
3.3 4.2 5.9 2.4 7.6
2.8 3.9 5.5 1.8 6.3
3.7 4.6 6.1 3.2 6.7
2.9 4.3 5.8 2.5 6.4
2.3 3.1 4.5 1.6 5
1.9 2.7 4.1 1.6 4.4
2.2 3.1 4.5 1.5 5.2
2.5 3.3 4.9 2 5.2
0.5
0.3
0.2
0.3
MIN MAX UNIT
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Page 7
SN74FB2031
9-BIT TTL/BTL ADDRESS/DATA TRANSCEIVER
SCBS176K – NOVEMBER 1991 – REVISED SEPTEMBER 1999
PARAMETER MEASUREMENT INFORMATION
2.1 V
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT FOR A OUTPUTS
Input
Input 1.5 V 1.5 V
Output
PROPAGATION DELAY TIMES (A TO B)
Input
Output
PROPAGATION DELAY TIMES (B TO A)
1.5 V 1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
500 Ω
500 Ω
t
w
t
PHL
t
PHL
1.5 V 1.5 V
7 V
S1
1.55 V1.55 V
1.55 V1.55 V
GND
t
PLH
t
PLH
Open
3 V
0 V
3 V
0 V
V
V
2 V
1 V
V
V
From Output
Under Test
CL = 30 pF
(see Note A)
LOAD CIRCUIT FOR B OUTPUTS
Timing Input
Data Input
OH
OL
OH
OL
Output
Control
Output
Waveform 1
S1 at 7 V
(see Note B)
Output
Waveform 2
S1 at Open
(see Note B)
ENABLE AND DISABLE TIMES (A PORT)
16.5 Ω
Test
Point
t
su
1.5 V 1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
1.5 V 1.5 V
t
PZL
1.5 V
t
PZH
1.5 V
VOLTAGE WAVEFORMS
TEST S1
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
1.5 V
t
h
t
PLZ
VOL + 0.3 V
t
PHZ
VOH – 0.3 V
Open
7 V
Open
3 V
0 V
3 V
0 V
3 V
0 V
3.5 V
V
OL
V
OH
≈ 0 V
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: TTL inputs: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns,
tf≤ 2.5 ns; BTL inputs: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
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7
Page 8
IMPORTANT NOTICE
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any product or service without notice, and advise customers to obtain the latest version of relevant information
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pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICA TIONS USING SEMICONDUCT OR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
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Copyright 1999, Texas Instruments Incorporated
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