Datasheet SN74FB1653PCA Datasheet (Texas Instruments)

D

Compatible With IEEE Std 1 194.1-1991
(BTL)

D

LVTTL A Port, Backplane Transceiver Logic
(BTL) B Port

D

Open-Collector B-Port Outputs Sink
100 mA

D

B-Port Biasing Network Preconditions the
Connector and PC Trace to the BTL
High-Level Voltage

SN74FB1653

17-BIT LVTTL/BTL UNIVERSAL STORAGE TRANSCEIVER

WITH BUFFERED CLOCK LINE

SCBS702C – AUGUST 1997 – REVISED SEPTEMBER 1999

D

High-Impedance State During Power Up
and Power Down

D

Selectable Clock Delay

D

TTL-Input Structures Incorporate Active
Clamping Networks to Aid in Line
Termination

D

BIAS VCC Minimizes Signal Distortion
During Live Insertion/Withdrawal

D

Packaged in Plastic High-Power
Low-Profile Quad Flatpack

PCA PACKAGE

(TOP VIEW)

VCC(3.3 V)

V

(5 V)

CC

GND

1AO6

1AI6

1AO7

1AI7

GND

1AO8

1AI8

1AO9

1AI9

GND

2CLK

(3.3 V)

V

CC

2AO2

2AI2

GND

2AO3

2AI3

2AO4

2AI4
GND
(5 V)

V

CC

(3.3 V)

V

CC

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

1AI5

1AO5

99

100

27

26

1AI4

98

28

1AO4

GND

96

97

30

29

1AI3

1AO3

94

95

32

31

1AI2

93

33

GND

1AO2

91

92

35

34

1AI1

1AO12AI9

89

90

37

36

(5 V)

CC

V

1OEA

87

88

39

38

1OEA

1LEBA

85

86

41

40

1CLKAB

1LEAB

1CLKBA

82

83

84

44

43

42

1OEB

1OEB

80

81

46

45

CC

REF

BG GND/GND

BG V

V

77

78

79

49

48

47

1B1

76

75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

50

1B2
GND
1B3
1B4
GND
1B5
1B6
GND
1B7
1B8
GND
1B9
2SEL2
2CLKAB
GND
2B2
2B3
GND
2B4
2B5
GND
2B6
2B7
GND
2B8

2AI5

2AO5

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

2AI6

2AO6

2AI8

2AI7

GND

2AO7

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2AO8

GND

2AO9

(5 V)

2OEA

CC

V

2OEA

2LEBA

2CLKBA

2CLKAB

2OEB

2LEAB

CC

2B9

GND

2OEB

2SEL1

BIAS V

Copyright  1999, Texas Instruments Incorporated

1

SN74FB1653

FUNCTION

B-bus isolation

A-bus isolation

FUNCTION

17-BIT LVTTL/BTL UNIVERSAL STORAGE TRANSCEIVER
WITH BUFFERED CLOCK LINE

SCBS702C – AUGUST 1997 – REVISED SEPTEMBER 1999

description

The SN74FB1653 device contains an 8-bit and a 9-bit transceiver with a buffered clock. The clock and
transceivers are designed to translate signals between L VTTL and BTL environments. It is specifically designed
to be compatible with IEEE Std 1194.1-1991 (BTL).

The A port operates at L VTTL signal levels. The A outputs reflect the inverse of the data at the B port when the
A-port output enable (OEA) is high. When OEA is low or when V
are in the high-impedance state.

port operates at BTL signal levels. The open-collector B ports are specified to sink 100 mA. Two output

The B
enables (OEB and OEB

) are provided for the B outputs. When OEB is low, OEB is high, or VCC(5 V) is typically

less than 2.5 V, the B port is turned off.
The clock-select inputs (2SEL1 and 2SEL2) are used to configure the TTL-to-BTL clock paths and delays. Refer

to the

Mux-Mode Delay

table.

(5 V) is typically less than 2.5 V , the A outputs

CC

BIAS V

establishes a voltage between 1.62 V and 2.1 V on the BTL outputs when VCC(5 V) is not connected.

CC

BG VCC and BG GND are the supply inputs for the bias generator.
V

is used to bypass the internal threshold reference voltage of the device. It is recommended that this pin

REF

be decoupled with a 0.1-µF capacitor.
Enhanced heat-dissipation techniques should be used when operating this device from: (a) AI to A0 at

frequencies greater than 50 MHz, or (b) AI to B, or B to A0 at frequencies greater than 100 MHz.
The SN74FB1653 is characterized for operation from 0°C to 70°C.

Function Tables

TRANSCEIVER

INPUTS

OEA OEA OEB OEB

X X H L A data to B bus
L HXX B data to A bus
L HHLA data to B bus, B data to A bus
X X L X
X XXH
H X X X
X L X X

STORAGE MODE

INPUTS

LE CLK

H X Transparent

L ↑ Store data
L L Storage

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

functional block diagram

SN74FB1653

17-BIT LVTTL/BTL UNIVERSAL STORAGE TRANSCEIVER

WITH BUFFERED CLOCK LINE

SCBS702C – AUGUST 1997 – REVISED SEPTEMBER 1999

1OEB

1OEB

1CLKAB

1LEAB

1LEBA

1CLKBA

1OEA
1OEA

1AI1

1AO1

81

80

83

82

85

84

87
86

90

89

C1

1D
C2

1D
C2

C1

76

1B1

To Eight Other Channels

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3

SN74FB1653
17-BIT LVTTL/BTL UNIVERSAL STORAGE TRANSCEIVER
WITH BUFFERED CLOCK LINE

SCBS702C – AUGUST 1997 – REVISED SEPTEMBER 1999

functional block diagram (continued)

2OEB

2OEB

2CLKAB

2LEAB

2LEBA

2CLKBA

2OEA
2OEA

2SEL2

2SEL1

2CLK

63

48

45

46

43

44

41

42

39
40

14

Delay3

Delay2

M
U
X

M

U
X

Delay1

62

2CLKAB

2AI2

2AO2

17

16

1D
C2

C1

1D
C2

C1

To Seven Other Channels

MUX-MODE DELAY

INPUTS

2SEL1 2SEL2 2CLKAB TO 2CLKAB 2CLKAB TO 2CLK

L L No delay No delay

L H No delay Delay1
H L Delay2 Delay1
H H Delay3 Delay1

†

Refer to delay1 through delay3 in the functional block diagram.

DELAY PATH

†

60

2B2

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

VIHHigh-level input voltage

V

VILLow-level input voltage

V

IOLLow-level output current

mA

SN74FB1653

17-BIT LVTTL/BTL UNIVERSAL STORAGE TRANSCEIVER

WITH BUFFERED CLOCK LINE

SCBS702C – AUGUST 1997 – REVISED SEPTEMBER 1999

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

†

Supply voltage range: VCC(5 V), BIAS VCC, BG VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

VCC(3.3 V) –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, V

: Except B port –1.2 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I

B port –1.2 V to 3.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input clamp current, IIK: Except B port –40 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

B port –18 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage range applied to any B output in the disabled or power-off state –0.5 V to 3.5 V. . . . . . . . . . . . . . . . . .

Voltage range applied to any output in the high state –0.5 V to V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC

Current applied to any single output in the low state: A port 48 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

B port 200 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Package thermal impedance, θJA (see Note 1) 22°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: The package thermal impedance is calculated in accordance with JESD 51.

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

recommended operating conditions (see Note 2)

MIN NOM MAX UNIT

V

CC,

BG VCC,
BIAS V

CC

VCC(3.3 V) Supply voltage 3 3.3 3.6 V

I

IK

I

OH

T

A

NOTE 2: To ensure proper device operation, all unused inputs must be terminated as follows: control inputs to VCC(5 V) or GND, A inputs to

VCC(5 V) only, and B inputs to GND only. Refer to the TI application report,
number SCBA004.

Supply voltage 4.5 5 5.5 V

p

p

Input clamp current –18 mA
High-level output current AO port –3 mA

p

Operating free-air temperature 0 70 °C

B port 1.62 2.3
Except B port 2
B port 0.75 1.47
Except B port 0.8

AO port 24
B port 100

Implications of Slow or Floating CMOS Inputs

, literature

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5

SN74FB1653

V

CC

() ,

VOHAO port

CC

() ,

V

B

CC

() ,

I

‡

A

VCC(3.3 V) = 3.3 V

17-BIT LVTTL/BTL UNIVERSAL STORAGE TRANSCEIVER
WITH BUFFERED CLOCK LINE

SCBS702C – AUGUST 1997 – REVISED SEPTEMBER 1999

electrical characteristics over recommended operating free-air temperature range

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

IK

V

OL

I

I

‡

I

IH

IL

I

OH

I

OZH

I

OZL

I

OZPU

I

OZPD

ICC(5 V)

ICC(3.3 V) B port to AO port
C

i

C

o

C

io

†

All typical values are at VCC(5 V) = 5 V and VCC(3.3 V) = 3.3 V, TA = 25°C.

‡

For I/O ports, the parameters IIH and IIL include the off-state output current.

B port
Except B port

p

AO port

port

Except B port

Except B port

Except B port

B port

B port

AO port

AO port
AO port VCC = 0 to 2.1 V, VO = 0.5 V to 2.7 V –50 µA

AO port VCC = 2.1 V to 0, VO = 0.5 V to 2.7 V –50 µA
AI port to B port
B port to AO port
Outputs disabled

Control and AI inputs VI = 0.5 V or 2.5 V 6.5 pF
AO port VO = 0.5 V or 2.5 V 3.5 pF

B port
per IEEE Std 1194.1-1991

V

(5 V) = 4.5 V,

VCC(3.3 V) = 3.3 V
V

(5 V) = 4.5 V,

VCC(3.3 V) = 3 V
VCC(5 V) = 4.5 V,

VCC(3.3 V) = 3 V
V

(5 V) = 4.5 V,

VCC(3.3 V) = 3 V
VCC(5 V) = 5.5 V,

VCC(3.3 V) = 3.6 V
VCC(5 V) = 5.5 V,

VCC(3.3 V) = 3.6 V
VCC(5 V) = 5.5 V,

VCC(3.3 V) = 3.6 V
VCC(5 V) = 5.5 V,

VCC(3.3 V) = 3.6 V
VCC(5 V) = 0 to 5.5 V,

VCC(3.3 V) = 3.6 V
VCC(5 V) = 5.5 V,

VCC(3.3 V) = 3.6 V
VCC(5 V) = 5.5 V,

VCC(3.3 V) = 3.6 V

VCC(5 V) = 5.5 V,

VCC(5 V) = 5.5 V,
VCC(3.3 V) = 3.3 V

VCC(5 V) = 0 to 5.5 V,
VCC(3.3 V) = 3.3 V

II = –18 mA –1.2 V
II = –40 mA –0.5 V
IOH = –1 mA
IOH = –3 mA 2.5

IOL = 24 mA 0.35 0.5
IOL = 80 mA 0.75 1.1

IOL = 100 mA 1.15
VI = 5.5 V 50 µA

VI = 2.7 V 50 µA

VI = 0.5 V –50

VI = 0.75 V –100

VO = 2.1 V 100 µA

VO = 2.7 V 50 µA

VO = 0.5 V –50 µA

IO = 0

IO = 0 1 mA

145
130
120

6.5 pF

V

µ

mA

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

I

(BIAS VCC)

V

V

(BIAS VCC)

V

A

twPulse duration

ns

tsuSetup time

ns

thHold time

ns

SN74FB1653

17-BIT LVTTL/BTL UNIVERSAL STORAGE TRANSCEIVER

WITH BUFFERED CLOCK LINE

SCBS702C – AUGUST 1997 – REVISED SEPTEMBER 1999

live-insertion specifications over recommended operating free-air temperature range

PARAMETER TEST CONDITIONS MIN MAX UNIT

VCC(5 V) = 0 to 4.5 V,
VCC(3.3 V) = 3.3 V

VCC(5 V) = 4.5 V to 5.5 V,
VCC(3.3 V) = 3.3 V

VCC(5 V) = 0,
VCC(3.3 V)= 0 V

VCC(5 V) = 0,
VCC(3.3 V) = 0 V

VCC(5 V) = 0 to 5.5 V,
VCC(3.3 V) = 3.3 V

VCC(5 V) = 0 to 2.2 V,
VCC(3.3 V) = 3.3 V

= 0 to 2 V,

B

VI (BIAS VCC) = 5 V 1.62 2.1 V

VB = 1 V, VI (BIAS VCC) = 4.5 V to 5.5 V –1

OEB = 0 to 0.8 V 100

OEB = 0 to 5 V 100

I

= 4.5 V to 5.5

V

I

CC

O

O

B port

B port

timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)

MIN MAX UNIT

f

clock

Clock frequency 90 MHz

LE high 3
CLK high or low 3

p

AI or B before LE↓ 3.5
AI or B before CLK↑ 3.5

AI or B after LE↓ 1
AI or B after CLK↑ 0.7

450

µ

10

µA

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

7

SN74FB1653

AI

B

ns

LEAB

B

ns

CLKAB

B

ns

2CLKAB

ns

2CLKAB

ns

2CLKAB

ns

B

AO

ns

LEBA

AO

ns

CLKBA

AO

ns

2CLK

ns

2CLK

ns

OEB

OEB

B

ns

OEA

OEA

AO

ns

OEA

OEA

AO

ns

†

ns

ns

‡

ns

t

ns

17-BIT LVTTL/BTL UNIVERSAL STORAGE TRANSCEIVER
WITH BUFFERED CLOCK LINE

SCBS702C – AUGUST 1997 – REVISED SEPTEMBER 1999

switching characteristics over recommended operating free-air temperature range,
V

(5 V) = 5 V ± 0.5 V and VCC(3.3 V) = 3.3 V (see Figure 1)

CC

PARAMETER

f

max

t

PLH

t

PHL

t

PLH

t

PHL

t

PLH

t

PHL

t

PLH

t

PHL

t

PLH

t

PHL

t

PLH

t

PHL

t

PLH

t

PHL

t

PLH

t

PHL

t

PLH

t

PHL

t

PLH

t

PHL

t

PLH

t

PHL

t

PLH

t

PHL

t

PZH

t

PZL

t

PHZ

t

PLZ

t

sk(p)

t

sk(p)

t

, t

sk(HL)

t

sk(o)

t

sk(o)

t

t

†

Skew values are applicable for through mode only, with single-output switching.

‡

Skew values are applicable for CLK mode only, with all outputs simultaneously switching high-to-low or low-to-high.

PR

sk(LH)

‡

†

Pulse skew, AI to B or B to AO 1.6
Pulse skew, 2CLKAB to 2CLK 1.8
Pulse skew, CLKAB to B or CLKBA to AO 1.5
Pulse skew, CLKAB to 2CLKAB 1.4
Pulse skew, AI to B or B to AO 1 ns
Pulse skew, non-delayed mode for 2CLKAB, CLKAB to AO 1
Pulse skew, non-delayed mode for 2CLKAB, CLKAB to B and 2CLKAB 1
Pulse skew, non-delayed mode for 2CLKAB, CLKAB to B and 2CLKAB 1.5 ns
Transition time, B outputs (1.3 V to 1.8 V) 0.5 4.6
Transition time, AO outputs (10% to 90%) 0.4 4.2
B-port input pulse rejection 1 ns

FROM

(INPUT)

2CLKAB

(no delay)

2CLKAB
(delay2)

2CLKAB
(delay3)

2CLKAB
(delay1)

2CLKAB

(no delay)

or

or

or

TO

(OUTPUT)

MIN MAX UNIT

90 MHz

1.8 6.2

2.9 6.6

2.7 6.9

3.5 7.3

2.3 6.4

2.9 6.7

2.3 6

2.9 6.7

4.5 9.5

4.5 9.5

9.3 15.4

9.3 15.4
2 6.5
2 6.5

1.8 6.3

1.8 6.3

1.8 6.3

1.8 6.3

5.7 12.3

5.7 12.3
2 6.5
2 6.5

2.6 7

2.6 7

1.4 5.5

1.4 5.5

1.4 6.5

1.4 5.8

8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN74FB1653

17-BIT LVTTL/BTL UNIVERSAL STORAGE TRANSCEIVER

WITH BUFFERED CLOCK LINE

SCBS702C – AUGUST 1997 – REVISED SEPTEMBER 1999

PARAMETER MEASUREMENT INFORMATION

2.1 V

From Output

Under Test

CL = 50 pF

(see Note A)

Input

Input

t

PHL

Output

Input

t

PHL

Output

500 Ω

500 Ω

LOAD CIRCUIT FOR A OUTPUTS

t

w

1.5 V 1.5 V

VOLTAGE WAVEFORMS

PULSE DURATION

1.5 V 1.5 V

1.55 V 1.55 V

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES (A to B)

1.55 V 1.55 V

1.5 V 1.5 V

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES (B to A)

S1

6 V

Open

GND

t

PLH

t

PLH

3 V

0 V

3 V

0 V

V

V

2 V

1 V

V

V

From Output

Under Test

CL = 30 pF

(see Note A)

LOAD CIRCUIT FOR B OUTPUTS

Timing Input

Data Input

OH

OL

OH

OL

Output

Control

(see Note B)

Output

Waveform 1

S1 at 6 V

(see Note B)

Output

Waveform 2

S1 at GND

(see Note B)

16.5 Ω

Test
Point

1.5 V 1.5 V

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

1.5 V 1.5 V

t

PZL

t

PZH

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES (A port)

t

su

1.5 V

1.5 V

TEST

t

PLH/tPHL

t

PLZ/tPZL

t

PHZ/tPZH

1.5 V

t

h

t

PLZ

VOL + 0.3 V

t

PHZ

VOH – 0.3 V

S1

Open

6 V

GND

3 V

0 V

3 V

0 V

3 V

0 V

3 V

V

OL

V

OH

≈ 0 V

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: TTL inputs – PRR ≤10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns,

tf≤ 2.5 ns. BTL inputs – PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 1 ns, tf≤ 1 ns.

D. The outputs are measured one at a time with one transition per measurement.

Figure 1. Load Circuits and Voltage Waveforms

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

9

IMPORTANT NOTICE

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any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.

CERTAIN APPLICA TIONS USING SEMICONDUCT OR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
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BE FULLY AT THE CUSTOMER’S RISK.

In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.

Copyright  1999, Texas Instruments Incorporated