Datasheet SN74CBTLV3857DBQR, SN74CBTLV3857DGVR, SN74CBTLV3857DW, SN74CBTLV3857DWR, SN74CBTLV3857PWR Datasheet (Texas Instruments)

SN74CBTLV3857

LOW-VOLTAGE 10-BIT FET BUS SWITCH

WITH INTERNAL PULLDOWN RESISTORS

SCDS085B – OCTOBER 1998 – REVISED AUGUST 1999

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D

Enable Signal Is SSTL_2 Compatible

D

Flow-Through Architecture Optimizes PCB
Layout

D

Designed for Use With 200 Mbit/s Double
Data-Rate (DDR) SDRAM Applications

D

Switch On-State Resistance Is Designed to
Eliminate Series Resistor to DDR SDRAM

D

Internal 10-kΩ Pulldown Resistors to
Ground on B Port

D

Internal 50-kΩ Pullup Resistor on
Output-Enable Input

D

Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II

D

Package Options Include Shrink
Small-Outline (DBQ), Thin Very
Small-Outline (DGV), Small-Outline (DW),
and Thin Shrink Small-Outline (PW)
Packages

description

This 10-bit FET bus switch is designed for 3-V to 3.6-V VCC operation and SSTL_2 output-enable (OE) input
levels.

When OE is low, the 10-bit bus switch is on, and port A is connected to port B. When OE is high, the switch is
open, and the high-impedance state exists between the two ports. There are 10-kΩ pulldown resistors to ground
on the B port.

The FET switch on-state resistance is designed to replace the series terminating resistor in the SSTL_2 data
path.

The SN74CBTLV3857 is characterized for operation from –40°C to 85°C.

FUNCTION TABLE

INPUT

OE

FUNCTION

L A port = B port

H Disconnect

Copyright  1999, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

DBQ, DGV, DW, OR PW PACKAGE

(TOP VIEW)

V

REF

A1
A2
A3
A4
A5
A6
A7
A8
A9

A10

GND

V

CC

OE
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10

1
2
3
4
5
6
7
8
9
10
11
12

24
23
22
21
20
19
18
17
16
15
14
13

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SN74CBTLV3857
LOW-VOLTAGE 10-BIT FET BUS SWITCH
WITH INTERNAL PULLDOWN RESISTORS

SCDS085B – OCTOBER 1998 – REVISED AUGUST 1999

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

logic diagram (positive logic)

A1

SW

B1

A10

SW

B10

OE

V

REF

R

INT

R

INT

V

CC

2

11

23
1

22

13

simplified schematic, each FET switch

A

(OE)

B

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

†

Supply voltage range, VCC –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range (OE only), VI (see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range (except OE), VI (see Note 1) –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous channel current 48 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input clamp current, I

IK

(V

I/O

< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Package thermal impedance, θJA (see Note 2): DBQ package 103°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DGV package 139°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DW package 81°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PW package 120°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.

2. The package thermal impedance is calculated in accordance with JESD 51.

SN74CBTLV3857

LOW-VOLTAGE 10-BIT FET BUS SWITCH

WITH INTERNAL PULLDOWN RESISTORS

SCDS085B – OCTOBER 1998 – REVISED AUGUST 1999

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

recommended operating conditions (see Note 3)

MIN NOM MAX UNIT

V

CC

Supply voltage 3 3.3 3.6 V

V

REF

Reference voltage (0.38 × VCC) 1.15 1.25 1.35 V

V

IH

AC high-level control input voltage V

REF

+ 350 mV V

V

IL

AC low-level control input voltage V

REF

– 350 mV V

V

IH

DC high-level control input voltage V

REF

+ 180 mV V

V

IL

DC low-level control input voltage V

REF

– 180 mV V

T

A

Operating free-air temperature –40 85 °C

NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,

Implications of Slow or Floating CMOS Inputs

, literature number SCBA004.

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

V

IK

VCC = 3 V, II = –18 mA –1.2 V
OE ±1 mA
A port

±5 µA

I

I

B port

V

CC

=

3.6 V

,

V

I

=

V

CC

or GND

±1 mA

V

REF

±5 µA

I

CC

VCC = 3.6 V, IO = 0, VI = VCC or GND 25 mA

C

i

Control inputs VI = 3 V or 0 3.5 pF

C

io(OFF)

VO = 3 V or 0, OE = V

CC

5 pF
VI = 0, II = 24 mA 5 8
VI = 0.9 V, II = 24 mA 6 11

r

on

‡

V

CC

= 3

V

VI = 1.25 V , II = 24 mA 7 13

Ω

VI = 1.6 V, II = 24 mA 9 40

VCC = 0 1

r

off

‡

VCC = 3 V to 3.6 V, VI = 1.65 V , OE = V

CC

1

MΩ

†

All typical values are at VCC = 3.3 V, TA = 25°C.

‡

Measured by the voltage drop between the A and B terminals at the indicated current through the switch. Resistance is determined by the lower
of the voltages of the two (A or B) terminals.

switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 1)

PARAMETER

FROM

TO

VCC = 3.3 V

± 0.3 V

UNIT

(INPUT)

(OUTPUT)

MIN MAX

t

pd

§

A or B B or A 0.25 ns

t

en

OE

A or B 1.4 4.2 ns

t

dis

OE

A or B 1.4 4.8 ns

§

The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance when
driven by an ideal voltage source (zero output impedance).

SN74CBTLV3857
LOW-VOLTAGE 10-BIT FET BUS SWITCH
WITH INTERNAL PULLDOWN RESISTORS

SCDS085B – OCTOBER 1998 – REVISED AUGUST 1999

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

V

CC

= 3.3 V ± 0.3 V AND V

DDQ

= 2.5 ± 0.2 V

V

DDQ

/2

V

DDQ

/2

V

REF

†

V

REF

†

V

OH

V

OL

From Output

Under Test

CL = 50 pF

(see Note A)

LOAD CIRCUIT

S1

Open

GND

500 Ω

500 Ω

Output

Control

Output

Waveform 1

S1 at 2 × V

DDQ

(see Note B)

Output

Waveform 2

S1 at GND

(see Note B)

t

PZL

t

PZH

t

PLZ

t

PHZ

VIL (AC)

§

VOL + 0.15 V

VOH – 0.15 V

0 V

VIH (AC)

‡

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

t

pd

t

PLZ/tPZL

t

PHZ/tPZH

Open

V

DDQ

× 2

GND

TEST S1

†

V

REF

= 0.38 × V

CC

‡

VIH(AC) = V

REF

+ 350 mV

§

VIL(AC) = V

REF

– 350 mV

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. t

PLZ

and t

PHZ

are the same as t

dis

.

F. t

PZL

and t

PZH

are the same as ten.

G. t

PLH

and t

PHL

are the same as tpd.

t

PHL

V

DDQ

/2 V

DDQ

/2

V

DDQ

0 V

V

OH

V

OL

Input

Output

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

V

DDQ

/2 V

DDQ

/2

t

PLH

V

DDQ

× 2

V

DDQ

Figure 1. Load Circuit and Voltage Waveforms

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pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.

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DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
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Copyright  1999, Texas Instruments Incorporated