Page 1
SN74CBTLV1G125
LOW-VOLTAGE SINGLE FET BUS SWITCH
SCDS057C – MARCH 1998 – REVISED JANUARY 2000
D
5-Ω Switch Connection Between Two Ports
D
Isolation Under Power-Off Conditions
D
Packaged in Plastic Small-Outline
Transistor Package
description
DBV PACKAGE
(TOP VIEW)
OE
A
GND
1
2
3
V
5
B
4
The SN74CBTLV1G125 features a single
high-speed line switch. The switch is disabled
when the output-enable (OE
T o ensure the high-impedance state during power up or power down, OE
) input is high.
should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN74CBTLV1G125 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
INPUT
OE
L A port = B port
H Disconnect
FUNCTION
logic diagram (positive logic)
OE
2
1
4
BA SW
CC
simplified schematic, each FET switch
A
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
B
(OE)
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 2000, Texas Instruments Incorporated
1
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SN74CBTLV1G125
VIHHigh-level control input voltage
V
VILLow-level control input voltage
V
V
0
TYP at V
CC
V
¶
Ω
V
0
LOW-VOLTAGE SINGLE FET BUS SWITCH
SCDS057C – MARCH 1998 – REVISED JANUARY 2000
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, VCC –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous channel current 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O
Package thermal impedance, θJA (see Note 2) 347°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51.
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
recommended operating conditions (see Note 3)
MIN MAX UNIT
V
T
NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Supply voltage 2.3 3.6 V
CC
p
p
Operating free-air temperature –40 85 °C
A
Implications of Slow or Floating CMOS Inputs
, literature number SCBA004.
VCC = 2.3 V to 2.7 V 1.7
VCC = 2.7 V to 3.6 V 2
VCC = 2.3 V to 2.7 V 0.7
VCC = 2.7 V to 3.6 V 0.8
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP‡MAX UNIT
V
IK
I
I
I
off
I
CC
§
∆I
C
C
r
on
‡
All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25°C.
§
This is the increase in supply current for each input that is at the specified voltage level rather than VCC or GND.
¶
Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by
the lower of the voltages of the two (A or B) terminals.
Control inputs VCC = 3.6 V, One input at 3 V, Other inputs at VCC or GND 300 µA
CC
Control inputs VI = 3 V or 0 2.5 pF
i
io(OFF)
VCC = 3 V, II = –18 mA –1.2 V
VCC = 3.6 V, VI = VCC or GND ±1 µA
VCC = 0, VI or VO = 0 to 3.6 V 10 µA
VCC = 3.6 V, IO = 0, VI = VCC or GND 10 µA
VO = 3 V or 0, OE = V
VCC = 2.3 V,
= 2.5
VCC = 3 V
=
I
VI = 1.7 V, II = 15 mA 15 25
=
I
VI = 2.4 V, II = 15 mA 10 15
CC
II = 64 mA 7 10
II = 24 mA 7 10
II = 64 mA 5 7
II = 24 mA 5 7
7 pF
2
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(INPUT)
(OUTPUT)
SN74CBTLV1G125
LOW-VOLTAGE SINGLE FET BUS SWITCH
SCDS057C – MARCH 1998 – REVISED JANUARY 2000
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 1 and 2)
PARAMETER
†
t
pd
t
en
t
†
The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and a load capacitance of 50 pF , when
driven by an ideal voltage source (zero output impedance).
dis
FROM
A or B B or A 0.35 0.25 ns
OE A or B 1 4 1 4 ns
OE A or B 1 5 1 4.1 ns
TO
VCC = 2.5 V
± 0.2 V
MIN MAX MIN MAX
PARAMETER MEASUREMENT INFORMATION
= 2.5 V ± 0.2 V
V
CC
VCC = 3.3 V
± 0.3 V
UNIT
dis
S1
.
From Output
Under Test
CL = 30 pF
(see Note A)
LOAD CIRCUIT
Input
t
PLH
Output
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. t
F. t
G. t
VCC/2 VCC/2
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
PLZ
PZL
PLH
and t
and t
and t
are the same as t
PHZ
are the same as ten.
PZH
are the same as tpd.
PHL
500 Ω
500 Ω
VCC/2 VCC/2
t
PHL
2 × V
Open
GND
V
0 V
V
V
CC
CC
OH
OL
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2 × V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
TEST S1
t
pd
t
PLZ/tPZL
t
PHZ/tPZH
t
PZL
CC
t
PZH
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VCC/2
VCC/2
Open
2 × V
GND
CC
VCC/2VCC/2
t
PLZ
VOL + 0.15 V
t
PHZ
VOH – 0.15 V
V
0 V
V
V
V
0 V
CC
CC
OL
OH
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SN74CBTLV1G125
LOW-VOLTAGE SINGLE FET BUS SWITCH
SCDS057C – MARCH 1998 – REVISED JANUARY 2000
PARAMETER MEASUREMENT INFORMATION
V
CC
2 × V
CC
Open
GND
From Output
Under Test
CL = 50 pF
(see Note A)
500 Ω
500 Ω
LOAD CIRCUIT
S1
= 3.3 V ± 0.3 V
Output
Control
TEST S1
t
pd
t
PLZ/tPZL
t
PHZ/tPZH
Open
2 × V
GND
CC
V
VCC/2VCC/2
CC
0 V
Input
t
PLH
Output
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. t
F. t
G. t
VCC/2 VCC/2
VCC/2 VCC/2
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
PLZ
PZL
PLH
and t
and t
and t
are the same as t
PHZ
are the same as ten.
PZH
are the same as tpd.
PHL
dis
.
Figure 2. Load Circuit and Voltage Waveforms
t
PHL
V
0 V
V
V
CC
OH
OL
Output
Waveform 1
S1 at 2 × V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
t
PZL
CC
t
PZH
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VCC/2
VCC/2
t
PLZ
VOL + 0.3 V
t
PHZ
VOH – 0.3 V
V
V
V
0 V
CC
OL
OH
4
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Page 5
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
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DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
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intellectual property right of TI covering or relating to any combination, machine, or process in which such
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party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 2000, Texas Instruments Incorporated
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