Datasheet SN74AVC16244DGGR, SN74AVC16244DGVR Datasheet (Texas Instruments)

SN74AVC16244

16-BIT BUFFER/DRIVER

WITH 3-STATE OUTPUTS

SCES141K – JULY 1998 – REVISED FEBRUAR Y 2000

D

Member of the Texas Instruments

D

Widebus EPIC

 Family

 (Enhanced-Performance Implanted

CMOS) Submicron Process

D

DOC

 (Dynamic Output Control) Circuit

Dynamically Changes Output Impedance, Resulting in Noise Reduction Without Speed Degradation

D

Less Than 2-ns Maximum Propagation Delay at 2.5-V and 3.3-V V

D

Dynamic Drive Capability Is Equivalent to Standard Outputs With I ±24 mA at 2.5-V V

CC

and IOL of

OH

description

A Dynamic Output Control (DOC) circuit is implemented, which, during the transition, initially lowers the output impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. Figure 1 shows typical V circuit. At the beginning of the signal transition, the DOC circuit provides a maximum dynamic drive that is equivalent to a high-drive standard-output device. For more information, refer to the TI application reports,

Logic Family T echnology and Applications Circuitry Technology and Applications

vs IOL and VOH vs IOH curves to illustrate the output impedance and drive capability of the

OL

, literature number SCEA006, and

, literature number SCEA009.

D

Overvoltage-Tolerant Inputs/Outputs Allow Mixed-Voltage-Mode Data Communications

D

I

Supports Partial-Power-Down Mode

off

Operation

D

ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A)

D

Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II

D

Package Options Include Plastic Thin Shrink Small-Outline (DGG) and Thin Very Small-Outline (DGV) Packages

Dynamic Output Control (DOC)

AVC

3.2

2.8

2.4

2.0

1.6

1.2

– Output Voltage – V

OL

0.8

V

0.4

TA = 25°C Process = Nominal

VCC = 1.8 V

IOL – Output Current – mA

VCC = 2.5 V

VCC = 3.3 V

136

17015311910285685134170

2.8

2.4

2.0

1.6

1.2

– Output Voltage – V

OH

0.8

V

0.4

TA = 25°C Process = Nominal

VCC = 3.3 V

–128–144–160

IOH – Output Current – mA

VCC = 2.5 V

VCC = 1.8 V

–80–96–112 –32–48–64 0–16

Figure 1. Output Voltage vs Output Current

This 16-bit buffer/driver is operational at 1.2-V to 3.6-V VCC, but is designed specifically for 1.65-V to 3.6-V V operation.

The SN74AVC16244 is designed specifically to improve the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters.

The device can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer . It provides true outputs and symmetrical active-low output-enable (OE) inputs.

CC

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

DOC, EPIC, and Widebus are trademarks of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

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Copyright  2000, Texas Instruments Incorporated

1

SN74AVC16244 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS

SCES141K – JULY 1998 – REVISED FEBRUAR Y 2000

description (continued)

T o ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This device is fully specified for partial-power-down applications using I

off

preventing damaging current backflow through the device when it is powered down. The SN74AVC16244 is characterized for operation from –40°C to 85°C.

terminal assignments

DGG OR DGV PACKAGE

(TOP VIEW)

1OE

1Y1 1Y2

GND

1Y3 1Y4

V

CC

2Y1 2Y2

GND

2Y3 2Y4 3Y1 3Y2

GND

3Y3 3Y4

V

CC

4Y1 4Y2

GND

4Y3 4Y4

4OE

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25

2OE 1A1 1A2 GND 1A3 1A4 V

CC

2A1 2A2 GND 2A3 2A4 3A1 3A2 GND 3A3 3A4 V

CC

4A1 4A2 GND 4A3 4A4 3OE

. The I

circuitry disables the outputs,

off

FUNCTION TABLE

(each 4-bit buffer)

INPUTS

OE A

L L L L HH

H X Z

2

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OUTPUT

Y

SN74AVC16244

16-BIT BUFFER/DRIVER

WITH 3-STATE OUTPUTS

SCES141K – JULY 1998 – REVISED FEBRUAR Y 2000

logic symbol

†

1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4 3A1 3A2 3A3 3A4 4A1 4A2 4A3 4A4

1 48 25 24

47 46 44 43 41 40 38 37 36 35 33 32 30 29 27 26

EN1 EN2 EN3 EN4

11 12 13 14 16 17 19 20 22 23

2

1Y1

3

1Y2

5

1Y3

6

1Y4

8

2Y1

9

2Y2 2Y3 2Y4 3Y1 3Y2 3Y3 3Y4 4Y1 4Y2 4Y3 4Y4

1

2

1

3

1

4

1OE 2OE

3OE 4OE

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

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3

SN74AVC16244 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS

SCES141K – JULY 1998 – REVISED FEBRUAR Y 2000

logic diagram (positive logic)

1OE

1A1

1A2

1A3

1A4

2OE

2A1

2A2

2A3

2A4

1

47

46

44

43

48

41

40

38

37

12

25

3OE

2

1Y1

3

1Y2

5

1Y3

6

1Y4

8

2Y1

9

2Y2

11

2Y3

2Y4

3A1

3A2

3A3

3A4

4OE

4A1

4A2

4A3

4A4

36

35

33

32

24

30

29

27

26

13

14

16

17

19

20

22

23

3Y1

3Y2

3Y3

3Y4

4Y1

4Y2

4Y3

4Y4

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, VCC –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, VI (see Note 1) –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage range applied to any output in the high-impedance or power-off state, V

(see Note 1) –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage range applied to any output in the high or low state, V

O

(see Notes 1 and 2) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input clamp current, IIK (VI < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output clamp current, I

(VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

OK

Continuous output current, IO ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous current through each VCC or GND ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Package thermal impedance, θJA (see Note 3): DGG package 70°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DGV package 58°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.

2. The output positive-voltage rating may be exceeded up to 4.6 V maximum if the output current rating is observed.

3. The package thermal impedance is calculated in accordance with JESD 51.

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

O

†

4

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VCCSuppl

oltage

V

VOOutput voltage

V

I

Static high-level output current

†

mA

I

Static low-level output current

†

mA

SN74AVC16244

16-BIT BUFFER/DRIVER

WITH 3-STATE OUTPUTS

SCES141K – JULY 1998 – REVISED FEBRUAR Y 2000

recommended operating conditions (see Note 4)

MIN MAX UNIT

pp

y v

V

OHS

OLS

∆t/∆v Input transition rise or fall rate VCC = 1.4 V to 3.6 V 5 ns/V T

†

Dynamic drive capability is equivalent to standard outputs with IOH and IOL of ±24 mA at 2.5-V VCC. See Figure 1 for VOL vs IOL and V characteristics. Refer to the TI application reports,

Dynamic Output Control (DOC) Circuitry Technology and Applications

NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,

High-level input voltage

IH

Low-level input voltage

IL

Input voltage 0 3.6 V

I

p

Operating free-air temperature –40 85 °C

A

AVC Logic Family Technology and Applications

Implications of Slow or Floating CMOS Inputs

, literature number SCBA004.

Operating 1.4 3.6 Data retention only 1.2 VCC = 1.2 V V VCC = 1.4 V to 1.6 V 0.65 × V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V 1.7 VCC = 3 V to 3.6 V 2 VCC = 1.2 V GND VCC = 1.4 V to 1.6 V 0.35 × V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V 0.7 VCC = 3 V to 3.6 V 0.8

Active state 0 V 3-state 0 3.6 VCC = 1.4 V to 1.6 V –2 VCC = 1.65 V to 1.95 V –4 VCC = 2.3 V to 2.7 V –8 VCC = 3 V to 3.6 V –12 VCC = 1.4 V to 1.6 V 2 VCC = 1.65 V to 1.95 V 4 VCC = 2.3 V to 2.7 V 8 VCC = 3 V to 3.6 V 12

, literature number SCEA009.

CC

0.65 × V

CC

0.35 × V

CC

, literature number SCEA006, and

CC CC

OH

V

vs I

OH

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5

SN74AVC16244

Control inputs

V

or GND

C

pF

Data inputs

V

or GND

CoOut uts

V

O

V

CC

GND

F

(INPUT)

(OUTPUT)

PARAMETER

TEST CONDITIONS

UNIT

C

pF

16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS

SCES141K – JULY 1998 – REVISED FEBRUAR Y 2000

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS

I

OHS

I

OHS

V

OH

V

OL

I I I I

†

Typical values are measured at TA = 25°C.

Control inputs VI = VCC or GND 3.6 V ±2.5 µA

I off OZ CC

p

i

p

I

OHS

I

OHS

I

OHS

I

OLS

I

OLS

I

OLS

I

OLS

I

OLS

VI or VO = 3.6 V 0 ±10 µA VO = VCC or GND 3.6 V ±10 µA VI = VCC or GND, IO = 0 3.6 V 40 µA

=

I

=

I

=

V

CC

= –100 µA 1.4 V to 3.6 V VCC–0.2 = –2 mA, VIH = 0.91 V 1.4 V 1.05 = –4 mA, VIH = 1.07 V 1.65 V 1.2 = –8 mA, VIH = 1.7 V 2.3 V 1.75

= –12 mA, VIH = 2 V 3 V 2.3 = 100 µA 1.4 V to 3.6 V 0.2 = 2 mA, VIL = 0.49 V 1.4 V 0.4 = 4 mA, VIL = 0.57 V 1.65 V 0.45 = 8 mA, VIL = 0.7 V 2.3 V 0.55 = 12 mA, VIL = 0.8 V 3 V 0.7

CC

or

2.5 V 3.5

3.3 V 3.5

2.5 V 6

3.3 V 6

2.5 V 6.5

3.3 V 6.5

MIN TYP†MAX UNIT

V

p

switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figures 2 through 5)

PARAMETER

t

pd

t

en

t

dis

FROM

A Y 3.1 0.6 3.3 0.7 2.9 0.6 1.9 0.5 1.7 ns OE OE

operating characteristics, T

Power dissipation

pd

capacitance

TO

Y 7.6 1.4 8 1.3 6.8 0.9 4 0.7 3.5 ns Y 7.2 1.7 7.3 1.6 6.2 1 4.3 1 3.5 ns

A

Outputs enabled Outputs disabled

VCC = 1.2 V

TYP MIN MAX MIN MAX MIN MAX MIN MAX

= 25°C

VCC = 1.5 V

± 0.1 V

= 0,f = 10 MHz

L

VCC = 1.8 V

± 0.15 V

VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V

TYP TYP TYP

VCC = 2.5 V

± 0.2 V

23 27 33

0.1 0.1 0.1

VCC = 3.3 V

± 0.3 V

UNIT

p

6

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From Output

Under Test

CL = 15 pF

(see Note A)

SCES141K – JULY 1998 – REVISED FEBRUAR Y 2000

PARAMETER MEASUREMENT INFORMATION

= 1.2 V AND 1.5 V ± 0.1 V

V

CC

2 × V

Open

GND

CC

TEST S1

t

pd

t

PLZ/tPZL

t

PHZ/tPZH

2 kΩ

S1

SN74AVC16244

16-BIT BUFFER/DRIVER

WITH 3-STATE OUTPUTS

Open

2 × V

CC

GND

LOAD CIRCUIT

Timing

Input

t

Data

Input

t

PLH

Output

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. t

PLZ

F. t

PZL

G. t

PLH

VCC/2

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

VCC/2 VCC/2

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

and t

PHZ

and t

PZH

and t

PHL

VCC/2

t

su

are the same as t are the same as ten.

are the same as tpd.

h

VCC/2

VCC/2 VCC/2

.

dis

t

PHL

V

0 V

V

0 V

V

0 V

V

CC

OH

OL

Input

Output

Control (low-level enabling)

Output

Waveform 1

S1 at 2 × V

(see Note B)

Output

Waveform 2

S1 at GND

(see Note B)

VOLTAGE WAVEFORMS

PULSE DURATION

t

PZL

CC

t

PZH

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

VCC/2

t

w

V

0 V

V

0 V

V

0 V

CC

OL

OH

VCC/2VCC/2

t

PLZ

VOL + 0.1 V

t

PHZ

VOH – 0.1 V

Figure 2. Load Circuit and Voltage Waveforms

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7

SN74AVC16244 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS

SCES141K – JULY 1998 – REVISED FEBRUAR Y 2000

PARAMETER MEASUREMENT INFORMATION

From Output

Under Test

CL = 30 pF

(see Note A)

1 kΩ

S1

= 1.8 V ± 0.15 V

V

CC

2 × V

CC

Open

GND

TEST S1

t

pd

t

PLZ/tPZL

t

PHZ/tPZH

Open

2 × V

GND

CC

LOAD CIRCUIT

Timing

Input

t

Data

Input

t

PLH

Output

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. t

PLZ

F. t

PZL

G. t

PLH

VCC/2

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

VCC/2 VCC/2

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

and t

PHZ

and t

PZH

and t

PHL

VCC/2

t

su

are the same as t are the same as ten.

h

VCC/2

VCC/2 VCC/2

dis

are the same as tpd.

.

t

PHL

V

0 V

V

0 V

V

0 V

V

CC

OH

OL

Input

Output

Control

(low-level

enabling)

Output

Waveform 1

S1 at 2 × V

(see Note B)

Output

Waveform 2

S1 at GND

(see Note B)

VOLTAGE WAVEFORMS

PULSE DURATION

t

PZL

CC

t

PZH

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

VCC/2

t

w

V

0 V

V

0 V

V

0 V

CC

OL

OH

VCC/2VCC/2

t

PLZ

VOL + 0.15 V

t

PHZ

VOH – 0.15 V

Figure 3. Load Circuit and Voltage Waveforms

8

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From Output

Under Test

CL = 30 pF

(see Note A)

SCES141K – JULY 1998 – REVISED FEBRUAR Y 2000

PARAMETER MEASUREMENT INFORMATION

= 2.5 V ± 0.2 V

V

CC

2 × V

500 Ω

S1

Open

GND

CC

TEST S1

t

pd

t

PLZ/tPZL

t

PHZ/tPZH

SN74AVC16244

16-BIT BUFFER/DRIVER

WITH 3-STATE OUTPUTS

Open

2 × V

CC

GND

LOAD CIRCUIT

Timing

Input

t

Data

Input

t

PLH

Output

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. t

PLZ

F. t

PZL

G. t

PLH

VCC/2

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

VCC/2 VCC/2

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

and t

PHZ

and t

PZH

and t

PHL

VCC/2

t

su

are the same as t are the same as ten.

are the same as tpd.

h

VCC/2

VCC/2 VCC/2

.

dis

t

PHL

V

0 V

V

0 V

V

0 V

V

CC

OH

OL

Input

Output

Control

(low-level

enabling)

Output

Waveform 1

S1 at 2 × V

(see Note B)

Output

Waveform 2

S1 at GND

(see Note B)

VOLTAGE WAVEFORMS

PULSE DURATION

t

PZL

CC

t

PZH

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

VCC/2

t

w

V

0 V

V

0 V

V

0 V

CC

OL

OH

VCC/2VCC/2

t

PLZ

VOL + 0.15 V

t

PHZ

VOH – 0.15 V

Figure 4. Load Circuit and Voltage Waveforms

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9

SN74AVC16244 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS

SCES141K – JULY 1998 – REVISED FEBRUAR Y 2000

PARAMETER MEASUREMENT INFORMATION

From Output

Under Test

CL = 30 pF

(see Note A)

500 Ω

S1

= 3.3 V ± 0.3 V

V

CC

2 × V

CC

Open

GND

TEST S1

t

pd

t

PLZ/tPZL

t

PHZ/tPZH

Open

2 × V

GND

CC

Timing

Input

Data

Input

Output

LOAD CIRCUIT

t

su

VCC/2 VCC/2

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

VCC/2

t

PLH

VCC/2 VCC/2

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

VCC/2

t

h

VCC/2

t

PHL

V

0 V

V

0 V

V

0 V

V

CC

OH

OL

Input

Output

Control

(low-level

enabling)

Output

Waveform 1

S1 at 2 × V

(see Note B)

Output

Waveform 2

S1 at GND

(see Note B)

t

w

VCC/2 VCC/2

VOLTAGE WAVEFORMS

PULSE DURATION

VCC/2

t

PZL

CC

t

PZH

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

VCC/2

VOL + 0.3 V

t

VOH – 0.3 V

t

PLZ

PHZ

V

0 V

V

0 V

V

0 V

CC

OL

OH

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. t F. t

G. t

PLZ PZL PLH

and t and t

and t

are the same as t

PHZ

are the same as ten.

PZH

are the same as tpd.

PHL

dis

Figure 5. Load Circuit and Voltage Waveforms

10

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.

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TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements.

CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICA TIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERST OOD TO BE FULLY AT THE CUSTOMER’S RISK.

In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.