Datasheet SN74AS4374BDW, SN74AS4374BDWR, SN74AS4374BN Datasheet (Texas Instruments)

SN74AS4374B

OCTAL EDGE-TRIGGERED D-TYPE DUAL-RANK FLIP-FLOP

WITH 3-STATE OUTPUTS

SDAS109D – APRIL 1989 – REVISED JANUARY 1995

Copyright  1995, Texas Instruments Incorporated

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

• 3-State Outputs Drive Bus Lines Directly

• Package Options Include Plastic

Small-Outline (DW) Packages and Standard
Plastic (N) 300-mil DIPs

description

This 8-bit flip-flop features 3-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. It is particularly
suitable for implementing buffer registers, I/O
ports, bidirectional bus drivers, and working
registers.

The eight flip-flops of the SN74AS4374B are
edge-triggered D-type flip-flops. On the second
positive transition of the clock (CLK) input, the Q
outputs are set to the logic levels set up at the data
(D) inputs.

The output-enable (OE

) input does not affect internal operations of the flip-flops. Previously stored data can be

retained or new data can be entered while the outputs are in the high-impedance state.
The SN74AS4374B is characterized for operation from 0°C to 70°C.

FUNCTION TABLE

(each flip-flop)

INPUTS

OUTPUT

OE CLK D

†

Q

H X X Z
L ↑ LL
L↑HH
LLXQ

0

†

Data presented at the D inputs require
two clock cycles to appear at the Q
outputs.

1
2
3
4
5
6
7
8
9
10

20
19
18
17
16
15
14
13
12
11

1Q
2Q
3Q
4Q

GND

5Q
6Q
7Q
8Q

OE

1D
2D
3D
4D
V

CC

5D
6D
7D
8D
CLK

DW OR N PACKAGE

(TOP VIEW)

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

SN74AS4374B
OCTAL EDGE-TRIGGERED D-TYPE DUAL-RANK FLIP-FLOP
WITH 3-STATE OUTPUTS

SDAS109D – APRIL 1989 – REVISED JANUARY 1995

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

logic symbol

†

logic diagram (positive logic)

1D

CLK

1Q

1

11

20

10

1D

C1

OE

OE

EN

10
11

CLK

1D

20

1D

19

2D

18

3D

17

4D

5Q

6

6Q

7

7Q

8

8Q

9

15

5D

14

6D

13

7D

12

8D

1Q

1

2Q

2

3Q

3

4Q

4

C1

To Seven Other Channels

1D

1D

C1

†

This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

‡

Supply voltage, V

CC

7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage, V

I

5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage applied to any output in the high state or power-off state, V

O

5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range, T

A

0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

‡

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

recommended operating conditions

MIN NOM MAX UNIT

V

CC

Supply voltage 4.5 5 5.5 V

V

IH

High-level input voltage 2 V

V

IL

Low-level input voltage 0.8 V

I

OH

High-level output current –15 mA

I

OL

Low-level output current 48 mA

T

A

Operating free-air temperature 0 70 °C

SN74AS4374B

OCTAL EDGE-TRIGGERED D-TYPE DUAL-RANK FLIP-FLOP

WITH 3-STATE OUTPUTS

SDAS109D – APRIL 1989 – REVISED JANUARY 1995

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

V

IK

VCC = 4.5 V, II = –18 mA –1.5 V

IOH = –3 mA 2.4 3.2

VOHV

CC

=

4.5 V

IOH = –15 mA 2

V

IOL = 32 mA 0.25 0.4

VOLV

CC

=

4.5 V

IOL = 48 mA 0.35 0.5

V

I

OZH

VCC = 5.5 V, VO = 2.7 V 20 µA

I

OZL

VCC = 5.5 V, VO = 0.4 V –20 µA

I

I

VCC = 5.5 V, VI = 7 V 0.1 mA

I

IH

VCC = 5.5 V, VI = 2.7 V 20 µA

I

IL

VCC = 5.5 V, VI = 0.5 V –0.2 mA

I

O

‡

VCC = 5.5 V, VO = 2.25 V –30 –112 mA

I

CC

VCC = 5.5 V, OE high 100 150 mA

†

All typical values are at VCC = 5 V, TA = 25°C.

‡

The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS.

timing requirements over recommended operating free-air temperature range (unless otherwise
noted)

MIN MAX UNIT

f

clock

Clock frequency 0 125 MHz

t

w

Pulse duration, CLK high or low 4 ns

t

su

Setup time, data before CLK↑ 4 ns

t

h

Hold time, data after CLK↑ 1 ns

switching characteristics (see Figure 1)

PARAMETER

FROM

(INPUT)

TO

(OUTPUT)

VCC = 4.5 V to 5.5 V,
CL = 50 pF,
R1 = 500 Ω

,

R2 = 500 Ω,
TA = MIN to MAX

§

UNIT

MIN MAX

f

max

125 MHz

t

PLH

2 8

t

PHL

CLK

Q

2 8

ns

t

PZH

1.5 6

t

PZL

OE

Q

2.5 8

ns

t

PHZ

2 6.5

t

PLZ

OE

Q

2.5 7

ns

§

For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.

SN74AS4374B
OCTAL EDGE-TRIGGERED D-TYPE DUAL-RANK FLIP-FLOP
WITH 3-STATE OUTPUTS

SDAS109D – APRIL 1989 – REVISED JANUARY 1995

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

t

PHZ

t

PLZ

t

PHL

t

PLH

0.3 V

t

PZL

t

PZH

t

PLH

t

PHL

LOAD CIRCUIT

FOR 3-STATE OUTPUTS

From Output

Under Test

Test Point

R1 = 500 Ω

S1

CL = 50 pF

(see Note A)

7 V

1.3 V

1.3 V1.3 V

3.5 V

3.5 V

0.3 V

0.3 V

t

h

t

su

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

Timing

Input

Data

Input

1.3 V 1.3 V

3.5 V

3.5 V

0.3 V

0.3 V

High-Level

Pulse

Low-Level

Pulse

t

w

VOLTAGE WAVEFORMS

PULSE DURATIONS

Input

Out-of-Phase

Output

1.3 V 1.3 V

1.3 V1.3 V

1.3 V 1.3 V

1.3 V1.3 V

1.3 V

1.3 V

3.5 V

3.5 V

0.3 V

0.3 V

V

OL

V

OH

V

OH

V

OL

Output

Control

Waveform 1

S1 Closed

(see Note B)

Waveform 2

S1 Open

(see Note B)

0 V

V

OH

V

OL

3.5 V

In-Phase

Output

0.3 V

1.3 V 1.3 V

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS

R2 = 500 Ω

Open

SWITCH POSITION TABLE

TEST S1

t

PLH

t

PHL

t

PZH

t

PZL

t

PHZ

t

PLZ

Open
Open
Open

Closed

Open

Closed

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.

Figure 1. Load Circuit and Voltage Waveforms

IMPORTANT NOTICE

T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.

CERT AIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICA TIONS IS UNDERST OOD TO
BE FULLY AT THE CUSTOMER’S RISK.

In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.

Copyright  1998, Texas Instruments Incorporated