Page 1
SN54ALVTH32244, SN74ALVTH32244
2.5-V/3.3-V 32-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCES279 – SEPTEMBER 1999
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
State-of-the-Art Advanced BiCMOS
Technology (ABT)
Widebus
Design for
2.5-V and 3.3-V Operation and Low Static
Power Dissipation
D
Support Mixed-Mode Signal Operation (5-V
Input and Output Voltages With 2.3-V to
3.6-V V
CC
)
D
T ypical V
OLP
(Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C
D
High Drive (–24/24 mA at 2.5-V VCC and
–32/64 mA at 3.3-V VCC)
D
I
off
and Power-Up 3-State Support Hot
Insertion
D
Use Bus Hold on Data Inputs in Place of
External Pullup/Pulldown Resistors to
Prevent the Bus From Floating
NOTE: For tape and reel order entry:
The GKER package is abbreviated to KR.
D
Auto3-State Eliminates Bus Current
Loading When Output Exceeds VCC + 0.5 V
D
Flow-Through Architecture Facilitates
Printed Circuit Board Layout
D
Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise
D
ESD Protection Exceeds JESD-22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
D
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
D
Packaged in Plastic Fine-Pitch Ball Grid
Array Package
description
The ’ALVTH32244 devices are 32-bit buffers/line drivers designed for 2.5-V or 3.3-V VCC operation, but with
the capability to provide a TTL interface to a 5-V system environment. These devices can be used as eight 4-bit
buffers, four 8-bit buffers, two 16-bit buffers, or one 32-bit buffer. These devices provide true outputs and
symmetrical active-low output-enable (OE
) inputs.
When V
CC
is between 0 and 1.2-V , the devices are in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 1.2-V, OE
should be tied to VCC through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.
These devices are fully specified for hot-insertion applications using I
off
and power-up 3-state. The I
off
circuitry
disables the outputs, preventing damaging current backflow through the devices when they are powered down.
The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN54ALVTH32244 is characterized for operation over the full military temperature range of –55°C to
125°C. The SN74ALVTH32244 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each 4-bit buffer)
INPUTS
OUTPUT
OE
A
Y
L H H
L LL
H X Z
Copyright 1999, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments Incorporated.
Page 2
SN54ALVTH32244, SN74ALVTH32244
2.5-V/3.3-V 32-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCES279 – SEPTEMBER 1999
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
terminal assignments
123456
A 1Y2
1Y1 1OE 2OE 1A1 1A2
B 1Y4 1Y3 GND GND 1A3 1A4
C 2Y2 2Y1 1V
CC
1V
CC
2A1 2A2
D 2Y4 2Y3 GND GND 2A3 2A4
E 3Y2 3Y1 GND GND 3A1 3A2
F 3Y4 3Y3 1V
CC
1V
CC
3A3 3A4
G 4Y2 4Y1 GND GND 4A1 4A2
H 4Y3 4Y4 4OE 3OE 4A4 4A3
J 5Y2 5Y1 5OE 6OE 5A1 5A2
K 5Y4 5Y3 GND GND 5A3 5A4
L 6Y2 6Y1 2V
CC
2V
CC
6A1 6A2
M 6Y4 6Y3 GND GND 6A3 6A4
N 7Y2 7Y1 GND GND 7A1 7A2
P 7Y4 7Y3 2V
CC
2V
CC
7A3 7A4
R 8Y2 8Y1 GND GND 8A1 8A2
T 8Y3 8Y4 8OE 7OE 8A4 8A3
GKE PACKAGE
(TOP VIEW)
J
H
G
F
E
D
C
B
A
213465
P
N
M
L
K
T
R
Page 3
SN54ALVTH32244, SN74ALVTH32244
2.5-V/3.3-V 32-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCES279 – SEPTEMBER 1999
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
1OE
1A1
1A2
1A3
1A4
1Y1
1Y2
1Y3
1Y4
A3
A5
A6
B5
B6
A2
A1
B2
B1
2OE
2A1
2A2
2A3
2A4
2Y1
2Y2
2Y3
2Y4
A4
C5
C6
D5
D6
C2
C1
D2
D1
3OE
3A1
3A2
3A3
3A4
3Y1
3Y2
3Y3
3Y4
H4
E5
E6
F5
F6
E2
E1
F2
F1
4OE
4A1
4A2
4A3
4A4
4Y1
4Y2
4Y3
4Y4
H3
G5
G6
H6
H5
G2
G1
H1
H2
NOTE A: 1VCC is associated with these channels.
Page 4
SN54ALVTH32244, SN74ALVTH32244
2.5-V/3.3-V 32-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCES279 – SEPTEMBER 1999
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
5OE
5A1
5A2
5A3
5A4
5Y1
5Y2
5Y3
5Y4
J3
J5
J6
K5
K6
J2
J1
K2
K1
6OE
6A1
6A2
6A3
6A4
6Y1
6Y2
6Y3
6Y4
J4
L5
L6
M5
M6
L2
L1
M2
M1
7OE
7A1
7A2
7A3
7A4
7Y1
7Y2
7Y3
7Y4
T4
N5
N6
P5
P6
N2
N1
P2
P1
8OE
8A1
8A2
8A3
8A4
8Y1
8Y2
8Y3
8Y4
T3
R5
R6
T6
T5
R2
R1
T1
T2
NOTE A: 2VCC is associated with these channels.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, VCC –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high-impedance
or power-off state, V
O
(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high state, VO (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . .
Current into any output in the low state, IO: SN54ALVTH32244 96 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SN74ALVTH32244 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current into any output in the high state, I
O
(see Note 2): SN54ALVTH32244 48 mA. . . . . . . . . . . . . . . . . . . .
SN74ALVTH32244 64 mA. . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
JA
(see Note 3) 40°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This current flows only when the output is in the high state and VO > VCC.
3. The package thermal impedance is calculated in accordance with JESD 51.
Page 5
SN54ALVTH32244, SN74ALVTH32244
2.5-V/3.3-V 32-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCES279 – SEPTEMBER 1999
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions, VCC = 2.5 V ± 0.2 V (see Note 4)
SN54ALVTH32244 SN74ALVTH32244
MIN MAX MIN MAX
UNIT
V
CC
Supply voltage 2.3 2.7 2.3 2.7 V
V
IH
High-level input voltage 1.7 1.7 V
V
IL
Low-level input voltage 0.7 0.7 V
V
I
Input voltage 0 5.5 0 5.5 V
I
OH
High-level output current –6 –8 mA
Low-level output current 6 8
I
OL
Low-level output current; current duty cycle ≤ 50%; f ≥ 1 kHz 18 24
mA
∆t/∆v Input transition rise or fall rate Outputs enabled 10 10 ns/V
∆t/∆V
CC
Power-up ramp rate 200 200 µs/V
T
A
Operating free-air temperature –55 125 –40 85 °C
NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs
, literature number SCBA004.
recommended operating conditions, VCC = 3.3 V ± 0.3 V (see Note 4)
SN54ALVTH32244 SN74ALVTH32244
MIN MAX MIN MAX
UNIT
V
CC
Supply voltage 3 3.6 3 3.6 V
V
IH
High-level input voltage 2 2 V
V
IL
Low-level input voltage 0.8 0.8 V
V
I
Input voltage 0 5.5 0 5.5 V
I
OH
High-level output current –24 –32 mA
Low-level output current 24 32
I
OL
Low-level output current; current duty cycle ≤ 50%; f ≥ 1 kHz 48 64
mA
∆t/∆v Input transition rise or fall rate Outputs enabled 10 10 ns/V
∆t/∆V
CC
Power-up ramp rate 200 200 µs/V
T
A
Operating free-air temperature –55 125 –40 85 °C
NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs
, literature number SCBA004.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
Page 6
SN54ALVTH32244, SN74ALVTH32244
2.5-V/3.3-V 32-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCES279 – SEPTEMBER 1999
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range,
V
CC
= 2.5 V ± 0.2 V (unless otherwise noted)
SN54ALVTH32244 SN74ALVTH32244
PARAMETER
TEST CONDITIONS
MIN TYP†MAX MIN TYP†MAX
UNIT
V
IK
VCC = 2.3 V, II = –18 mA –1.2 –1.2 V
VCC = 2.3 V to 2.7 V, IOH = –100 µA VCC–0.2 VCC–0.2
V
OH
IOH = –6 mA 1.8
V
V
CC
= 2.3
V
IOH = –8 mA 1.8
VCC = 2.3 V to 2.7 V, IOL = 100 µA 0.2 0.2
IOL = 6 mA 0.4
V
OL
IOL = 8 mA 0.4
V
V
CC
= 2.3
V
IOL = 18 mA 0.5
IOL = 24 mA 0.5
p
VCC = 2.7 V, VI = VCC or GND ±1 ±1
Control inputs
VCC = 0 or 2.7 V, VI = 5.5 V 10 10
I
I
p
VI = V
CC
1 1
µ
A
Data inputs
V
CC
=
2.7 V
VI = 0 –5 –5
I
off
VCC = 0, VI or VO = 0 to 4.5 V ±100 µA
I
BHL
‡
VCC = 2.3 V, VI = 0.7 V 115 115 µA
I
BHH
§
VCC = 2.3 V, VI = 1.7 V –10 –10 µA
I
BHLO
¶
VCC = 2.7 V, VI = 0 to V
CC
300 300 µA
I
BHHO
#
VCC = 2.7 V, VI = 0 to V
CC
–300 –300 µA
I
EX
||
VCC = 2.3 V, VO = 5.5 V 125 125 µA
I
OZ(PU/PD)
k
VCC ≤ 1.2 V, VO = 0.5 V to VCC,
VI = GND or VCC, OE
= don’t care
±100 ±100 µA
I
OZH
VCC = 2.7 V
VO = 2.3 V,
VI = 0.7 V or 1.7 V
5 5 µA
I
OZL
VCC = 2.7 V
VO = 0.5 V,
VI = 0.7 V or 1.7 V
–5 –5 µA
=
Outputs high 0.04 0.1 0.04 0.1
I
CC
V
CC
= 2.7 V,
IO = 0,
Outputs low 2.3 4.5 2.3 4.5
mA
VI = VCC or GND
Outputs disabled 0.04 0.1 0.04 0.1
C
i
VCC = 2.5 V, VI = 2.5 V or 0 3 3 pF
C
o
VCC = 2.5 V, VO = 2.5 V or 0 6 6 pF
†
All typical values are at VCC = 2.5 V, TA = 25°C.
‡
The bus-hold circuit can sink at least the minimum low sustaining current at VIL max. I
BHL
should be measured after lowering VIN to GND and
then raising it to VIL max.
§
The bus-hold circuit can source at least the minimum high sustaining current at VIH min. I
BHH
should be measured after raising VIN to VCC and
then lowering it to VIH min.
¶
An external driver must source at least I
BHLO
to switch this node from low to high.
#
An external driver must sink at least I
BHHO
to switch this node from high to low.
||
Current into an output in the high state when VO > V
CC
k
High-impedance state during power up or power down
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
Page 7
SN54ALVTH32244, SN74ALVTH32244
2.5-V/3.3-V 32-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCES279 – SEPTEMBER 1999
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range,
V
CC
= 3.3 V ± 0.3 V (unless otherwise noted)
SN54ALVTH32244 SN74ALVTH32244
PARAMETER
TEST CONDITIONS
MIN TYP†MAX MIN TYP†MAX
UNIT
V
IK
VCC = 3 V, II = –18 mA –1.2 –1.2 V
VCC = 3 V to 3.6 V, IOH = –100 µA VCC–0.2 VCC–0.2
V
OH
IOH = –24 mA 2
V
V
CC
= 3
V
IOH = –32 mA 2
VCC = 3 V to 3.6 V, IOL = 100 µA 0.2 0.2
IOL = 16 mA 0.4
IOL = 24 mA 0.5
V
OL
VCC = 3 V
IOL = 32 mA 0.5
V
IOL = 48 mA 0.55
IOL = 64 mA 0.55
p
VCC = 3.6 V, VI = VCC or GND ±1 ±1
Control inputs
VCC = 0 or 3.6 V, VI = 5.5 V 10 10
I
I
VI = 5.5 V 20 20
µA
Data inputs VCC = 3.6 V
VI = V
CC
1 1
VI = 0 –5 –5
I
off
VCC = 0, VI or VO = 0 to 4.5 V ±100 µA
I
BHL
‡
VCC = 3 V, VI = 0.8 V 75 75 µA
I
BHH
§
VCC = 3 V, VI = 2 V –75 –75 µA
I
BHLO
¶
VCC = 3.6 V, VI = 0 to V
CC
500 500 µA
I
BHHO
#
VCC = 3.6 V, VI = 0 to V
CC
–500 –500 µA
I
EX
||
VCC = 3 V, VO = 5.5 V 125 125 µA
I
OZ(PU/PD)
k
VCC ≤ 1.2 V, VO = 0.5 V to VCC,
VI = GND or VCC, OE
= don’t care
±100 ±100 µA
I
OZH
VCC = 3.6 V
VO = 3 V,
VI = 0.8 V or 2 V
5 5 µA
I
OZL
VCC = 3.6 V
VO = 0.5 V,
VI = 0.8 V or 2 V
–5 –5 µA
=
Outputs high 0.07 0.1 0.07 0.1
I
CC
V
CC
= 3.6 V,
IO = 0,
Outputs low 3.2 5 3.2 5
mA
VI = VCC or GND
Outputs disabled 0.07 0.1 0.07 0.1
∆I
CC
h
VCC = 3 V to 3.6 V, One input at VCC – 0.6 V,
Other inputs at VCC or GND
0.4 0.4 mA
C
i
VCC = 3.3 V, 3 3 pF
C
o
VCC = 3.3 V, 6 6 pF
†
All typical values are at VCC = 3.3 V, TA = 25°C.
‡
The bus-hold circuit can sink at least the minimum low sustaining current at VIL max. I
BHL
should be measured after lowering VIN to GND and
then raising it to VIL max.
§
The bus-hold circuit can source at least the minimum high sustaining current at VIH min. I
BHH
should be measured after raising VIN to VCC and
then lowering it to VIH min.
¶
An external driver must source at least I
BHLO
to switch this node from low to high.
#
An external driver must sink at least I
BHHO
to switch this node from high to low.
||
Current into an output in the high state when VO > V
CC
k
High-impedance state during power up or power down
h
This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
Page 8
SN54ALVTH32244, SN74ALVTH32244
2.5-V/3.3-V 32-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCES279 – SEPTEMBER 1999
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics over recommended operating free-air temperature range, CL = 30 pF,
V
CC
= 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1)
FROM TO
SN54ALVTH32244 SN74ALVTH32244
PARAMETER
(INPUT) (OUTPUT)
MIN MAX MIN MAX
UNIT
t
PLH
1 3.1 1 3
t
PHL
A
Y
1 3.6 1 3.5
ns
t
PZH
1.1 6 1.1 5.9
t
PZL
OE
Y
1.1 4.8 1.1 4.7
ns
t
PHZ
1.5 4.5 1.5 4.4
t
PLZ
OE
Y
1 3.5 1 3.4
ns
switching characteristics over recommended operating free-air temperature range, CL = 50 pF,
V
CC
= 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 2)
FROM TO
SN54ALVTH32244 SN74ALVTH32244
PARAMETER
(INPUT) (OUTPUT)
MIN MAX MIN MAX
UNIT
t
PLH
1 2.6 1 2.4
t
PHL
A
Y
1 2.6 1 2.5
ns
t
PZH
1 3.9 1 3.8
t
PZL
OE
Y
1 3 1 2.9
ns
t
PHZ
1.5 4.3 1.5 4.2
t
PLZ
OE
Y
1.5 3.7 1.5 3.6
ns
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
Page 9
SN54ALVTH32244, SN74ALVTH32244
2.5-V/3.3-V 32-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCES279 – SEPTEMBER 1999
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
V
CC
= 2.5 V ± 0.2 V
VCC/2
VCC/2
VCC/2VCC/2
VCC/2VCC/2
VCC/2
VCC/2
V
OH
V
OL
t
h
t
su
From Output
Under Test
CL = 30 pF
(see Note A)
LOAD CIRCUIT
S1
Open
GND
500 Ω
500 Ω
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2 × V
CC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
t
PZL
t
PZH
t
PLZ
t
PHZ
0 V
VOL + 0.15 V
VOH – 0.15 V
0 V
V
CC
0 V
0 V
t
w
V
CC
V
CC
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
Timing
Input
Data
Input
Input
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
Open
2 × V
CC
GND
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
0 V
V
CC
VCC/2
t
PHL
VCC/2 VCC/2
V
CC
0 V
V
OH
V
OL
Input
Output
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VCC/2 VCC/2
t
PLH
2 × V
CC
V
CC
Figure 1. Load Circuit and Voltage Waveforms
Page 10
SN54ALVTH32244, SN74ALVTH32244
2.5-V/3.3-V 32-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCES279 – SEPTEMBER 1999
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
V
CC
= 3.3 V ± 0.3 V
V
OH
V
OL
t
h
t
su
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1
Open
GND
500 Ω
500 Ω
t
PLH
t
PHL
Output Control
Output
Waveform 1
S1 at 6 V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
t
PZL
t
PZH
t
PLZ
t
PHZ
3 V
0 V
V
OH
V
OL
0 V
VOL + 0.3 V
VOH – 0.3 V
≈ 0 V
3 V
0 V
0 V
t
w
Input
3 V
3 V
3 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Timing
Input
Data
Input
Output
Input
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
Open
6 V
GND
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤10 MHz, ZO = 50 Ω, tr ≤2.5 ns, tf ≤2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
6 V
1.5 V
1.5 V 1.5 V
1.5 V 1.5 V
0 V
3 V
1.5 V 1.5 V
1.5 V 1.5 V
1.5 V
1.5 V
1.5 V 1.5 V
Figure 2. Load Circuit and Voltage Waveforms
Page 11
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