Datasheet SN74ALVTH16244DL, SN74ALVTH16244DLR, SN74ALVTH16244GR, SN74ALVTH16244VR Datasheet (Texas Instruments)

SN54ALVTH16244, SN74ALVTH16244

2.5-V/3.3-V 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

SCES070G – JUNE 1996 – REVISED MA Y 1999

D

Members of the Texas Instruments

Widebus

D

State-of-the-Art Advanced BiCMOS

 Family

Technology (ABT) Design for 3.3-V Operation and Low Static-Power Dissipation

D

5-V I/O Compatible

D

High Drive Capability (–32 mA/64 mA)

D

Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V V

D

Support Unregulated Battery Operation Down to 2.3 V

D

Typical V < 0.8 V at V

D

Auto3-State Eliminates Bus Current

(Output Ground Bounce)

OLP

= 3.3 V, TA = 25°C

CC

Loading When Voltage at the Output Exceeds V

D

I

off

and Power-Up 3-State Support Hot

CC

Insertion

D

Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors

D

Latch-Up Performance Exceeds 250 mA Per JESD 17

D

ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)

D

Package Options Include Plastic 300-mil Shrink Small-Outline (DL), Thin Shrink Small-Outline (DGG), Thin Very Small-Outline (DGV) Packages, and 380-mil Fine-Pitch Ceramic Flat (WD) Package

NOTE: For tape and reel order entry:

The DGGR package is abbreviated to GR, and the DGVR package is abbreviated to VR.

CC

SN54ALVTH16244.. . WD PACKAGE

SN74ALVTH16244.. . DGG, DGV, OR DL PACKAGE

)

1OE

1Y1 1Y2

GND

1Y3 1Y4

V

CC

2Y1 2Y2

GND

2Y3 2Y4 3Y1 3Y2

GND

3Y3 3Y4

V

CC

4Y1 4Y2

GND

4Y3 4Y4

4OE

(TOP VIEW)

1

48

2

47

3

46

4

45

5

44

6

43

7

42

8

41

9

40

10

39

11

38

12

37

13

36

14

35

15

34

16

33

17

32

18

31

19

30

20

29

21

28

22

27

23

26

24

25

2OE 1A1 1A2 GND 1A3 1A4 V

CC

2A1 2A2 GND 2A3 2A4 3A1 3A2 GND 3A3 3A4 V

CC

4A1 4A2 GND 4A3 4A4 3OE

description

The ’ALVTH16244 devices are 16-bit buffers/line drivers designed for 2.5-V or 3.3-V VCC operation, but with the capability to provide a TTL interface to a 5-V system environment. These devices can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Widebus is a trademark of Texas Instruments Incorporated.

UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  1999, Texas Instruments Incorporated

1

SN54ALVTH16244, SN74ALVTH16244

2.5-V/3.3-V 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

SCES070G – JUNE 1996 – REVISED MA Y 1999

description (continued)

When VCC is between 0 and 1.2 V , the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.2 V, the output-enable (OE through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

) input should be tied to V

CC

These devices are fully specified for hot-insertion applications using I

and power-up 3-state. The I

off

disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.

The SN54ALVTH16244 is characterized for operation over the full military temperature range of –55°C to 125°C. The SN74ALVTH16244 is characterized for operation from –40°C to 85°C.

FUNCTION TABLE

(each buffer)

INPUTS

OE

L H H L LL

HXZ

OUTPUT

A

Y

logic diagram (positive logic)

1OE

1A1

1A2

1

47

46

2

1Y1

3

1Y2

3OE

3A1

3A2

25

36

35

13

14

3Y1

3Y2

circuitry

off

1A3

1A4

2OE

2A1

2A2

2A3

2A4

44

43

48

41

40

38

37

11

12

5

1Y3

6

1Y4

8

2Y1

9

2Y2

2Y3

2Y4

3A3

3A4

4OE

4A1

4A2

4A3

4A4

33

32

24

30

29

27

26

16

17

19

20

22

23

3Y3

3Y4

4Y1

4Y2

4Y3

4Y4

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

UNIT

I

mA

SN54ALVTH16244, SN74ALVTH16244

2.5-V/3.3-V 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

SCES070G – JUNE 1996 – REVISED MA Y 1999

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V Input voltage range, V Voltage range applied to any output in

or power-off state, V Voltage range applied to any output in the high state, V Output current in the low state, I

–0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC

(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I

the high-impedance

(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

O

: SN54ALVTH16244 96 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

O

(see Note 1) –0.5 V to VCC to 7V. . . . . . . . . . . . . .

O

†

SN74ALVTH16244 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output current in the high state, I

: SN54ALVTH16244 –48 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

O

SN74ALVTH16244 –64 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input clamp current, I Output clamp current, I Package thermal impedance, θ

(V

< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

IK

I

(V

< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

OK

O

(see Note 2): DGG package 89°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

JA

DGV package 93°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DL package 94°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

2. The package thermal impedance is calculated in accordance with JESD 51.

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

recommended operating conditions, VCC = 2.5 V ± 0.2 V (see Note 3)

SN54ALVTH16244 SN74ALVTH16244

MIN MAX MIN MAX

V

CC

V

IH

V

IL

V

I

OH

OL

∆t/∆v Input transition rise or fall rate Outputs enabled 10 10 ns/V ∆t/∆V

T

A

NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,

Supply voltage 2.3 2.7 2.3 2.7 V High-level input voltage 1.7 1.7 V Low-level input voltage 0.7 0.7 V Input voltage 0 5.5 0 5.5 V High-level output current –6 –8 mA Low-level output current 6 8 Low-level output current; current duty cycle ≤ 50%; f ≥ 1 kHz 18 24

Power-up ramp rate 200 200 µs/V

CC

Operating free-air temperature –55 125 –40 85 °C

Implications of Slow or Floating CMOS Inputs

, literature number SCBA004.

PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3

SN54ALVTH16244, SN74ALVTH16244

UNIT

I

mA

2.5-V/3.3-V 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

SCES070G – JUNE 1996 – REVISED MA Y 1999

recommended operating conditions, VCC = 3.3 V ± 0.3 V (see Note 3)

SN54ALVTH16244 SN74ALVTH16244

MIN MAX MIN MAX

V

CC

V

IH

V

IL

V

I

OH

OL

∆t/∆v Input transition rise or fall rate Outputs enabled 10 10 ns/V ∆t/∆V

T

A

NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,

Supply voltage 3 3.6 3 3.6 V High-level input voltage 2 2 V Low-level input voltage 0.8 0.8 V Input voltage 0 5.5 0 5.5 V High-level output current –24 –32 mA Low-level output current 24 32 Low-level output current; current duty cycle ≤ 50%; f ≥ 1 kHz 48 64

Power-up ramp rate 200 200 µs/V

CC

Operating free-air temperature –55 125 –40 85 °C

Implications of Slow or Floating CMOS Inputs

, literature number SCBA004.

PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER

TEST CONDITIONS

UNIT

V

Control inputs

I

A

Data inputs

V

2.7 V

(

)

V

I(hold)

V

CC

SN54ALVTH16244, SN74ALVTH16244

2.5-V/3.3-V 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

SCES070G – JUNE 1996 – REVISED MA Y 1999

electrical characteristics over recommended operating free-air temperature range,

= 2.5 V ± 0.2 V (unless otherwise noted)

V

CC

SN54ALVTH16244 SN74ALVTH16244

MIN TYP†MAX MIN TYP†MAX

V

IK

V

OH

V

OL

I

p

I

off

hold

i o

Data inputs

§ ¶

I

EX

I

OZ(PU/PD)

I

OZH

I

OZL

I

CC

C C

†

All typical values are at VCC = 2.5 V, TA = 25°C.

‡

This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.

§

Current into an output in the high state when VO > V

¶

High-impedance state during power up/power down

VCC = 2.3 V, II = –18 mA –1.2 –1.2 V VCC = 2.3 V to 2.7 V, IOH = –100 µA VCC–0.2 VCC–0.2

= 2.3

CC

VCC = 2.3 V to 2.7 V, IOL = 100 µA 0.2 0.2

= 2.3

CC

VCC = 2.7 V, VI = VCC or GND ±1 ±1

p

VCC = 0 or 2.7 V, VI = 5.5 V 10 10

=

CC

VCC = 0, VI or VO = 0 to 4.5 V ±100 µA

= 2.3

CC

VCC = 2.7 V‡, VI = 0 to 2.7 V ±300 ±300 VCC = 2.3 V, VO = 5.5 V 125 125 µA VCC ≤ 1.2 V, VO = 0.5 V to VCC,

VI = GND or VCC, OE VCC = 2.7 V

VCC = 2.7 V

=

= 2.7 V, IO = 0, VI = VCC or GND

VCC = 2.5 V, VI = 2.5 V or 0 3 3 pF VCC = 2.5 V, VO = 2.5 V or 0 6 6 pF

IOH = –6 mA 1.8 IOH = –8 mA 1.8

IOL = 6 mA 0.4 IOL = 8 mA 0.4 IOL = 18 mA 0.5 IOL = 24 mA 0.5

VI = V

CC

VI = 0 –5 –5

VI = 0.7 V 115 115 VI = 1.7 V –10 –10

= don’t care

VO = 2.3 V, VI = 0.7 V or 1.7 V

VO = 0.5 V, VI = 0.7 V or 1.7 V

Outputs high 0.04 0.1 0.04 0.1 Outputs low 2.3 4.5 2.3 4.5 Outputs disabled 0.04 0.1 0.04 0.1

CC

1 1

±100 ±100 µA

5 5 µA

–5 –5 µA

V

µ

µA

mA

PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.

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5

SN54ALVTH16244, SN74ALVTH16244

PARAMETER

TEST CONDITIONS

UNIT

V

Control inputs

)

V

I(hold)

V

CC

2.5-V/3.3-V 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

SCES070G – JUNE 1996 – REVISED MA Y 1999

electrical characteristics over recommended operating free-air temperature range,

= 3.3 V ± 0.3 V (unless otherwise noted)

V

CC

SN54ALVTH16244 SN74ALVTH16244

MIN TYP†MAX MIN TYP†MAX

V

IK

V

OH

OL

I

Data inputs VCC = 3.6 V

I

off

CC

i o

Data inputs

§ ¶

#

I

I(hold

I

EX

I

OZ(PU/PD)

I

OZH

I

OZL

I

CC

∆I C

C

†

All typical values are at VCC = 3.3 V, TA = 25°C.

‡

This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.

§

Current into an output in the high state when VO > V

¶

High-impedance state during power up/power down

#

This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.

VCC = 3 V, II = –18 mA –1.2 –1.2 V VCC = 3 V to 3.6 V, IOH = –100 µA VCC–0.2 VCC–0.2

= 3

CC

VCC = 3 V to 3.6 V, IOL = 100 µA 0.2 0.2

VCC = 3 V

VCC = 3.6 V, VI = VCC or GND ±1 ±1

p

VCC = 0 or 3.6 V, VI = 5.5 V 10 10

VCC = 0, VI or VO = 0 to 4.5 V ±100 µA

= 3

CC

VCC = 3.6 V‡, VI = 0 to 3.6 V ±500 ±500 VCC = 3 V, VO = 5.5 V 125 125 µA VCC ≤ 1.2 V, VO = 0.5 V to VCC,

VI = GND or VCC, OE VCC = 3.6 V

VCC = 3.6 V

=

= 3.6 V, IO = 0, VI = VCC or GND

VCC = 3 V to 3.6 V, One input at VCC – 0.6 V, Other inputs at VCC or GND

VCC = 3.3 V, VI = 3.3 V or 0 3 3 pF VCC = 3.3 V, VO = 3.3 V or 0 6 6 pF

IOH = –24 mA 2 IOH = –32 mA 2

IOL = 16 mA 0.4 IOL = 24 mA 0.5 IOL = 32 mA 0.5 IOL = 48 mA 0.55 IOL = 64 mA 0.55

VI = 5.5 V 20 20 VI = V

CC

VI = 0 –5 –5

VI = 0.8 V 75 75 VI = 2 V –75 –75

= don’t care

VO = 3 V, VI = 0.8 V or 2 V

VO = 0.5 V, VI = 0.8 V or 2 V

Outputs high 0.07 0.1 0.07 0.1 Outputs low 3.2 5 3.2 5 Outputs disabled 0.07 0.1 0.07 0.1

CC

1 1

±100 ±100 µA

5 5 µA

–5 –5 µA

0.4 0.4 mA

V

µA

mA

PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.

6

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PARAMETER

UNIT

A

Y

ns

OE

Y

ns

OE

Y

ns

PARAMETER

UNIT

A

Y

ns

OE

Y

ns

OE

Y

ns

SN54ALVTH16244, SN74ALVTH16244

2.5-V/3.3-V 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

SCES070G – JUNE 1996 – REVISED MA Y 1999

switching characteristics over recommended operating free-air temperature range, CL = 30 pF,

= 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1)

V

CC

FROM TO

(INPUT) (OUTPUT)

t

PLH

t

PHL

t

PZH

t

PZL

t

PHZ

t

PLZ

switching characteristics over recommended operating free-air temperature range, CL = 50 pF,

= 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 2)

V

CC

FROM TO

(INPUT) (OUTPUT)

t

PLH

t

PHL

t

PZH

t

PZL

t

PHZ

t

PLZ

SN54ALVTH16244 SN74ALVTH16244

MIN MAX MIN MAX

1 3.1 1 3 1 3.6 1 3.5

1.1 6 1.1 5.9

1.1 4.8 1.1 4.7

1.5 4.5 1.5 4.4 1 3.5 1 3.4

SN54ALVTH16244 SN74ALVTH16244

MIN MAX MIN MAX

1 2.6 1 2.4 1 2.6 1 2.5 1 3.9 1 3.8 1 3 1 2.9

1.5 4.3 1.5 4.2

1.5 3.7 1.5 3.6

PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

7

SN54ALVTH16244, SN74ALVTH16244

2.5-V/3.3-V 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

SCES070G – JUNE 1996 – REVISED MA Y 1999

PARAMETER MEASUREMENT INFORMATION

From Output

Under Test

CL = 30 pF

(see Note A)

500 Ω

S1

V

= 2.5 V ± 0.2 V

CC

2 × V

CC

Open

GND

TEST S1

t

PLH/tPHL

t

PLZ/tPZL

t

PHZ/tPZH

Open

2 × V

GND

CC

LOAD CIRCUIT

Timing

Input

t

Data

Input

t

PLH

Output

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time with one transition per measurement.

VCC/2

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

VCC/2 VCC/2

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

VCC/2

t

su

h

VCC/2

VCC/2 VCC/2

t

PHL

V

0 V

V

0 V

V

0 V

V

CC

OH

OL

Input

Output

Control

(low-level

enabling)

Output

Waveform 1

S1 at 2 × V

(see Note B)

Output

Waveform 2

S1 at GND

(see Note B)

VOLTAGE WAVEFORMS

PULSE DURATION

t

PZL

CC

t

PZH

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

VCC/2

t

w

V

0 V

V

0 V

V

0 V

CC

OL

OH

VCC/2VCC/2

t

PLZ

VOL + 0.15 V

t

PHZ

VOH – 0.15 V

Figure 1. Load Circuit and Voltage Waveforms

8

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From Output

Under Test

CL = 50 pF

(see Note A)

SN54ALVTH16244, SN74ALVTH16244

2.5-V/3.3-V 16-BIT BUFFERS/DRIVERS

SCES070G – JUNE 1996 – REVISED MA Y 1999

PARAMETER MEASUREMENT INFORMATION

V

= 3.3 V ± 0.3 V

CC

6 V

500 Ω

S1

Open

GND

TEST S1

t

PLH/tPHL

t

PLZ/tPZL

t

PHZ/tPZH

WITH 3-STATE OUTPUTS

Open

6 V

GND

LOAD CIRCUIT

Timing

Input

Data

Input

Output

PROPAGATION DELAY TIMES

INVERTING AND NONINVERTING OUTPUTS

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤10 MHz, ZO = 50 Ω, tr ≤2.5 ns, tf ≤2.5 ns. D. The outputs are measured one at a time with one transition per measurement.

1.5 V 1.5 V

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

1.5 V 1.5 V

VOLTAGE WAVEFORMS

1.5 V

t

su

t

h

t

PLH

1.5 V 1.5 V

t

PHL

3 V

0 V

3 V

0 V

3 V

0 V

V

OH

OL

Input

Output Control

Output

Waveform 1

S1 at 6 V

(see Note B)

Output

Waveform 2

S1 at GND

(see Note B)

t

w

1.5 V 1.5 V

VOLTAGE WAVEFORMS

PULSE DURATION

1.5 V 1.5 V

t

PZL

1.5 V

t

PZH

1.5 V

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

LOW- AND HIGH-LEVEL ENABLING

VOL + 0.3 V

VOH – 0.3 V

t

PLZ

t

PHZ

3 V

0 V

3 V

0 V

3 V

V

OL

V

OH

≈ 0 V

Figure 2. Load Circuit and Voltage Waveforms

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9

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