Page 1
SN74ALVCHG162282
18-BIT TO 36-BIT REGISTERED BUS EXCHANGER
WITH 3-STATE OUTPUTS
SCES094C – FEBRUARY 1997 – REVISED JUNE 1999
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Member of the Texas Instruments
Widebus
Family
D
EPIC
(Enhanced-Performance Implanted
CMOS) Sub-Micron Process
D
A-Port Outputs Have Equivalent 50-Ω
Series Resistors and B-Port Outputs Have
Equivalent 20-Ω Series Resistors, So No
External Resistors Are Required
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D
Latch-Up Performance Exceeds 250 mA Per
JESD 17
D
Bus-Hold On Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D
Packaged in Thin Very Small-Outline
Package
NOTE: For order entry:
The DBB package is abbreviated to G.
For tape and reel:
The DBBR package is abbreviated to GR.
description
The SN74ALVCHG162282 is an 18-bit to 36-bit
registered bus exchanger. This device is intended
for use in applications where data must be
transferred from a narrow high-speed bus to a
wide lower-frequency bus. It is designed
specifically for low-voltage (3.3-V) V
CC
operation.
The device provides synchronous data exchange
between the two ports. Data is stored in the
internal registers on the low-to-high transition of
the clock (CLK) input. For data transfer in the
B-to-A direction, the select (SEL
) input selects 1B
or 2B data for the A outputs.
For data transfer in the A-to-B direction, a
two-stage pipeline is provided in the 1B path, with
a single storage register in the 2B path. Data flow
is controlled by the active-low output-enable (OE)
and direction-control (DIR) input. DIR is registered
to synchronize the bus direction changes with the
clock.
Copyright 1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus and EPIC are trademarks of Texas Instruments Incorporated.
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V
CC
GND
2B9
1B9
2B8
GND
1B8
2B7
1B7
V
CC
2B6
1B6
2B5
1B5
GND
2B4
1B4
2B3
1B3
V
CC
GND
2B2
1B2
2B1
1B1
V
CC
A1
A2
A3
GND
A4
A5
A6
V
CC
A7
A8
A9
GND
CLK
SEL
V
CC
GND
1B10
2B10
1B11
GND
2B11
1B12
2B12
V
CC
1B13
2B13
1B14
2B14
GND
1B15
2B15
1B16
2B16
V
CC
GND
1B17
2B17
1B18
2B18
V
CC
A18
A17
A16
GND
A15
A14
A13
V
CC
A12
A11
A10
GND
OE
DIR
DBB PACKAGE
(TOP VIEW)
Page 2
SN74ALVCHG162282
18-BIT TO 36-BIT REGISTERED BUS EXCHANGER
WITH 3-STATE OUTPUTS
SCES094C – FEBRUARY 1997 – REVISED JUNE 1999
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description (continued)
The A-port N-channel output transistors are sized at 450 µm and the P-channel output transistors are sized at
700 µm. All A-port outputs have equivalent 50-Ω series resistors. The B-port N-channel output transistors are
sized at 225 µm, and the P-channel output transistors are sized at 560 µm. All B-port outputs have equivalent
20-Ω series resistors.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The switching characteristics are based on 25-pF (A port) and 80-pF (B port) loads, but are tested with the
standard 50-pF load.
The SN74ALVCHG162282 is characterized for operation from 0°C to 70°C.
Function Tables
A-TO-B STORAGE
(OE
= L, DIR = H)
INPUTS
OUTPUTS
SEL CLK A 1B 2B
H X X 1B
0
†
2B
0
†
L ↑ LL‡L
L ↑ H H
‡
H
†
Output level before indicated
steady-state input conditions were
established
‡
Two CLK edges are needed to propagate
the data.
B-TO-A STORAGE
(OE
= L, DIR = L)
INPUTS
OUTPUT
CLK SEL 1B 2B
A
↑ H X L L
§
↑ HXH H
§
↑ LLX L
↑ L H X H
§
Two CLK edges are needed to propagate the
data. The data is loaded in the first register
when SEL
is low and propagates to the
second register when SEL
is high.
OUTPUT ENABLE
INPUTS
OUTPUTS
CLK OE DIR A 1B, 2B
↑ H X Z Z
↑ LHZActive
↑ L L Active Z
Page 3
SN74ALVCHG162282
18-BIT TO 36-BIT REGISTERED BUS EXCHANGER
WITH 3-STATE OUTPUTS
SCES094C – FEBRUARY 1997 – REVISED JUNE 1999
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
C1
1D
C1
1D
G1
1
1
C1
CE
1D
C1
CE
C1
CE
1D
1D
C1
CE
1D
1 of 18 Channels
39
40
42
41
27
25
24
CLK
SEL
OE
DIR
A1
1B1
2B1
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SN74ALVCHG162282
18-BIT TO 36-BIT REGISTERED BUS EXCHANGER
WITH 3-STATE OUTPUTS
SCES094C – FEBRUARY 1997 – REVISED JUNE 1999
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
†
Supply voltage range, VCC –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI: Except I/O ports (see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O ports (see Notes 1 and 2) –0.5 V to V
CC
+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, VO (see Notes 1 and 2) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
JA
(see Note 3) 106°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The input and output positive voltage ratings may be exceeded up to 4.6 V if the input and output clamp-current ratings are observed.
3. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions (see Note 4)
MIN MAX UNIT
V
CC
Supply voltage 3 3.6 V
V
IH
High-level input voltage VCC = 3 V to 3.6 V 2 V
V
IL
Low-level input voltage VCC = 3 V to 3.6 V 0.8 V
V
I
Input voltage 0 V
CC
V
V
O
Output voltage 0 V
CC
V
p
A to B VCC = 3 V 8
IOHHigh-level output current
B to A VCC = 3 V 6
mA
p
A to B VCC = 3 V 8
IOLLow-level output current
B to A VCC = 3 V 6
mA
∆t/∆v Input transition rise or fall rate 10 ns/V
T
A
Operating free-air temperature 0 70 °C
NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs
, literature number SCBA004.
Page 5
SN74ALVCHG162282
18-BIT TO 36-BIT REGISTERED BUS EXCHANGER
WITH 3-STATE OUTPUTS
SCES094C – FEBRUARY 1997 – REVISED JUNE 1999
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS V
CC
MIN TYP†MAX UNIT
IOH = –100 µA 3 V to 3.6 V VCC–0.2
V
OH
A to B IOH = –8 mA 3 V 2
V
B to A IOH = –6 mA 3 V 2
IOL = 100 µA 3 V to 3.6 V 0.2
V
OL
A to B IOL = 8 mA 3 V 0.8
V
B to A IOL = 6 mA 3 V 0.8
I
I
VI = VCC or GND 3.6 V ±5 µA
VI = 0.8 V 3 V 75
I
I(hold)
VI = 2 V 3 V –75
µA
()
VI = 0 to 3.6 V
‡
3.6 V ±500
I
OZ
§
VO = VCC or GND 3.6 V ±10 µA
I
CC
VI = VCC or GND, IO = 0 3.6 V 40 µA
∆I
CC
One input at VCC – 0.6 V, Other inputs at VCC or GND 3 V to 3.6 V 750 µA
C
i
Control inputs VI = VCC or GND 3.3 V 4 pF
C
io
A or B ports VO = VCC or GND 3.3 V 8.5 pF
†
All typical values are at VCC = 3.3 V, TA = 25°C.
‡
This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.
§
For I/O ports, the parameter IOZ includes the input leakage current.
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1)
VCC = 3.3 V
± 0.3 V
UNIT
MIN MAX
f
clock
Clock frequency 160 MHz
t
w
Pulse duration, CLK high or low 2.3 ns
A data before CLK↑ 1.5
p
B data before CLK↑ 2
tsuSetup time, high or lo
w
DIR before CLK↑
2
ns
SEL before CLK↑ 2
A data after CLK↑ 0.3
B data after CLK↑ 0.3
thHold time, high or lo
w
DIR after CLK↑
0.3
ns
SEL after CLK↑ 0.3
Page 6
SN74ALVCHG162282
18-BIT TO 36-BIT REGISTERED BUS EXCHANGER
WITH 3-STATE OUTPUTS
SCES094C – FEBRUARY 1997 – REVISED JUNE 1999
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics over recommended operating free-air temperature range,
C
L
= 25 pF (A port), 80 pF (B port) (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
VCC = 3.3 V
± 0.3 V
UNIT
(INPUT)
(OUTPUT)
MIN MAX
f
max
160 MHz
A 1.5 5
tpdCLK
B 1.5 7.4
ns
A 1.5 6.3
CLK
B 1.5 9.4
t
en
A 1.5 6
ns
OE
B 1.5 9.5
A 1.5 6.4
CLK
B 1.5 7.8
t
dis
A 1.5 5
ns
OE
B 1.5 7.6
Page 7
SN74ALVCHG162282
18-BIT TO 36-BIT REGISTERED BUS EXCHANGER
WITH 3-STATE OUTPUTS
SCES094C – FEBRUARY 1997 – REVISED JUNE 1999
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
V
OH
V
OL
t
h
t
su
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1
Open
GND
500 Ω
500 Ω
t
PLH
t
PHL
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 6 V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
t
PZL
t
PZH
t
PLZ
t
PHZ
2.7 V
0 V
V
OH
V
OL
0 V
VOL + 0.3 V
VOH – 0.3 V
0 V
2.7 V
0 V
0 V
t
w
Input
2.7 V
2.7 V
3 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
Timing
Input
Data
Input
Output
Input
t
pd
t
PLZ/tPZL
t
PHZ/tPZH
Open
6 V
GND
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The output is measured with one input transition per measurement.
E. t
PLZ
and t
PHZ
are the same as t
dis
.
F. t
PZL
and t
PZH
are the same as ten.
G. t
PLH
and t
PHL
are the same as tpd.
6 V
1.5 V
1.5 V 1.5 V
1.5 V 1.5 V
0 V
2.7 V
1.5 V 1.5 V
1.5 V 1.5 V
1.5 V
1.5 V
1.5 V 1.5 V
Figure 1. Load Circuit and Voltage Waveforms
Page 8
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performed, except those mandated by government requirements.
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Copyright 1999, Texas Instruments Incorporated
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