Datasheet SN74ALVCH374DBR, SN74ALVCH374DGVR, SN74ALVCH374DW, SN74ALVCH374DWR, SN74ALVCH374N Datasheet (Texas Instruments)

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SN74ALVCH374

OCTAL POSITIVE EDGE-TRIGGERED D-TYPE FLIP-FLOP

WITH 3-STATE OUTPUTS

SCES118E – JULY 1997 – REVISED OCTOBER 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

EPIC

 (Enhanced-Performance Implanted

CMOS) Submicron Process

Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors

Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II

ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101)

Package Options Include Plastic Small-Outline (DW), Thin Very Small-Outline (DGV), and Thin Shrink Small-Outline (PW) Packages

description

This octal edge-triggered D-type flip-flop is designed for 1.65-V to 3.6-V VCC operation. The SN74ALVCH374 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus

drivers, and working registers. On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels at the data (D) inputs.

A buffered output-enable (OE

) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly . The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.

does not affect internal operations of the latch. Old data can be retained or new data can be entered while

the outputs are in the high-impedance state. T o ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. The SN74ALVCH374 is characterized for operation from –40°C to 85°C.

FUNCTION TABLE

(each flip-flop)

INPUTS

OUTPUT

OE CLK D

L ↑ H H L ↑ LL L H or L X Q

H X X Z

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC is a trademark of Texas Instruments Incorporated.

DGV, DW, OR PW PACKAGE

(TOP VIEW)

1 2 3 4 5 6 7 8 9 10

20 19 18 17 16 15 14 13 12 11

1Q 1D 2D 2Q 3Q 3D 4D 4Q

GND

8Q 8D 7D 7Q 6Q 6D 5D 5Q CLK

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

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SN74ALVCH374 OCTAL POSITIVE EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS

SCES118E – JULY 1997 – REVISED OCTOBER 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

logic symbol

†

CLK

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

logic diagram (positive logic)

To Seven Other Channels

CLK

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

‡

Supply voltage range, VCC –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, VI (see Note 1) –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output voltage range, VO (see Notes 1 and 2) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input clamp current, I

(VI < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output clamp current, IOK (VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous output current, IO ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous current through VCC or GND ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Package thermal impedance, θ

(see Note 3): DGV package 92°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DW package 58°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PW package 83°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

‡

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.

2. This value is limited to 4.6 V maximum.

3. The package thermal impedance is calculated in accordance with JESD 51.

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SN74ALVCH374

OCTAL POSITIVE EDGE-TRIGGERED D-TYPE FLIP-FLOP

WITH 3-STATE OUTPUTS

SCES118E – JULY 1997 – REVISED OCTOBER 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

recommended operating conditions (see Note 4)

MIN MAX UNIT

Supply voltage 1.65 3.6 V

VCC = 1.65 V to 1.95 V 0.65 × V

High-level input voltage

VCC = 2.3 V to 2.7 V

1.7

V VCC = 2.7 V to 3.6 V 2 VCC = 1.65 V to 1.95 V 0.35 × V

Low-level input voltage

VCC = 2.3 V to 2.7 V

0.7

V VCC = 2.7 V to 3.6 V 0.8

Input voltage 0 V

Output voltage 0 V

V VCC = 1.65 V –4

VCC = 2.3 V –12

IOHHigh-level output current

VCC = 2.7 V –12

VCC = 3 V –24 VCC = 1.65 V 4

VCC = 2.3 V 12

IOLLow-level output current

VCC = 2.7 V 12

VCC = 3 V 24

∆t/∆v Input transition rise or fall rate 5 ns/V T

Operating free-air temperature –40 85 °C

NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,

Implications of Slow or Floating CMOS Inputs

, literature number SCBA004.

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SN74ALVCH374 OCTAL POSITIVE EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS

SCES118E – JULY 1997 – REVISED OCTOBER 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS

MIN TYP†MAX UNIT

IOH = –100 µA 1.65 V to 3.6 V VCC–0.2 IOH = –4 mA 1.65 V 1.2 IOH = –6 mA 2.3 V 2

2.3 V 1.7

IOH = –12 mA

2.7 V 2.2 3 V 2.4

IOH = –24 mA 3 V 2 IOL = 100 µA 1.65 V to 3.6 V 0.2 IOL = 4 mA 1.65 V 0.45 IOL = 6 mA 2.3 V 0.4

2.3 V 0.7

= 12

2.7 V 0.4

IOL = 24 mA 3 V 0.55

VI = VCC or GND 3.6 V ±5 µA VI = 0.58 V 1.65 V 25 VI = 1.07 V 1.65 V –25 VI = 0.7 V 2.3 V 45

I(hold)

VI = 1.7 V 2.3 V –45

µA

()

VI = 0.8 V 3 V 75 VI = 2 V 3 V –75 VI = 0 to 3.6 V

‡

3.6 V ±500

VO = VCC or GND 3.6 V ±10 µA

VI = VCC or GND, IO = 0 3.6 V 10 µA

∆I

One input at VCC – 0.6 V, Other inputs at VCC or GND 3 V to 3.6 V 750 µA

Control inputs

Data inputs

GND

3.3 V

Outputs VO = VCC or GND 3.3 V 7.5 pF

†

All typical values are at VCC = 3.3 V, TA = 25°C.

‡

This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.

timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 3)

VCC = 1.8 V

± 0.15 V

VCC = 2.5 V

± 0.2 V

VCC = 2.7 V

VCC = 3.3 V

± 0.3 V

UNIT

MIN MAX MIN MAX MIN MAX MIN MAX

clock

Clock frequency 100 100 150 MHz

Pulse duration, CLK high or low 3.8 3.3 3.3 3.3 ns

Setup time, data before CLK↑ 3 1.8 2.1 1.8 ns

Hold time, data after CLK↑ 1 0.5 0.5 0.5 ns

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SN74ALVCH374

OCTAL POSITIVE EDGE-TRIGGERED D-TYPE FLIP-FLOP

WITH 3-STATE OUTPUTS

SCES118E – JULY 1997 – REVISED OCTOBER 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 3)

PARAMETER

FROM

VCC = 1.8 V

± 0.15 V

VCC = 2.5 V

± 0.2 V

VCC = 2.7 V

VCC = 3.3 V

± 0.3 V

UNIT

(INPUT)

(OUTPUT)

MIN MAX MIN MAX MIN MAX MIN MAX

max

100 100 150 MHz

CLK

1.5 6.4 1 3.9 3.6 1.1 3.6 ns

3.6 8.1 2.1 5.6 5.3 1.6 5.2 ns

dis

2.7 7.9 0.9 4.5 4.4 1.2 4.5 ns

operating characteristics, T

= 25°C

VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V

PARAMETER

TEST CONDITIONS

TYP TYP TYP

UNIT

Power dissipation capacitance

Outputs enabled

44 46 50

per flip-flop

Outputs disabled

= 0,f = 10 MHz

24 26 29.5

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SN74ALVCH374 OCTAL POSITIVE EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS

SCES118E – JULY 1997 – REVISED OCTOBER 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

= 1.8 V ± 0.15 V

VCC/2

VCC/2VCC/2

From Output

Under Test

CL = 30 pF

(see Note A)

LOAD CIRCUIT

Open

GND

1 kΩ

Output

Control

(low-level

enabling)

Output

Waveform 1

S1 at 2 × V

(see Note B)

Output

Waveform 2

S1 at GND

(see Note B)

PZL

PZH

PLZ

PHZ

0 V

VOL + 0.15 V

VOH – 0.15 V

0 V

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

VOLTAGE WAVEFORMS

PULSE DURATION

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

Timing

Input

Data

Input

PLZ/tPZL

PHZ/tPZH

Open

2 × V

GND

TEST S1

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. t

PLZ

and t

PHZ

are the same as t

dis

F. t

PZL

and t

PZH

are the same as ten.

G. t

PLH

and t

PHL

are the same as tpd.

0 V

VCC/2

PHL

VCC/2 VCC/2

0 V

Input

Output

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

VCC/2 VCC/2

PLH

2 × V

Figure 1. Load Circuit and Voltage Waveforms

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SN74ALVCH374

OCTAL POSITIVE EDGE-TRIGGERED D-TYPE FLIP-FLOP

WITH 3-STATE OUTPUTS

SCES118E – JULY 1997 – REVISED OCTOBER 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

= 2.5 V ± 0.2 V

VCC/2

VCC/2VCC/2

From Output

Under Test

CL = 30 pF

(see Note A)

LOAD CIRCUIT

Open

GND

500 Ω

Output

Control (low-level enabling)

Output

Waveform 1

S1 at 2 × V

(see Note B)

Output

Waveform 2

S1 at GND

(see Note B)

PZL

PZH

PLZ

PHZ

0 V

VOL + 0.15 V

VOH – 0.15 V

0 V

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

VOLTAGE WAVEFORMS

PULSE DURATION

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

Timing

Input

Data

Input

PLZ/tPZL

PHZ/tPZH

Open

2 × V

GND

TEST S1

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr≤ 2 ns, tf≤ 2 ns. D. The outputs are measured one at a time with one transition per measurement.

E. t

PLZ

and t

PHZ

are the same as t

dis

F. t

PZL

and t

PZH

are the same as ten.

G. t

PLH

and t

PHL

are the same as tpd.

0 V

VCC/2

PHL

VCC/2 VCC/2

0 V

Input

Output

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

VCC/2 VCC/2

PLH

2 × V

Figure 2. Load Circuit and Voltage Waveforms

Page 8

SN74ALVCH374 OCTAL POSITIVE EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS

SCES118E – JULY 1997 – REVISED OCTOBER 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

= 2.7 V AND 3.3 V ± 0.3 V

PZL

PZH

From Output

Under Test

CL = 50 pF

(see Note A)

LOAD CIRCUIT

6 V

Open

GND

500 Ω

PLH

PHL

Output

Control

(low-level

enabling)

Output

Waveform 1

S1 at 6 V

(see Note B)

Output

Waveform 2

S1 at GND

(see Note B)

PLZ

PHZ

2.7 V

0 V

VOL + 0.3 V

VOH – 0.3 V

0 V

2.7 V

0 V

2.7 V

0 V

Input

2.7 V

3 V

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

VOLTAGE WAVEFORMS

PULSE DURATION

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

Timing

Input

Data

Input

Output

Input

PLZ/tPZL

PHZ/tPZH

Open

6 V

GND

TEST S1

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤2.5 ns, tf ≤2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. t

PLZ

and t

PHZ

are the same as t

dis

F. t

PZL

and t

PZH

are the same as ten.

G. t

PLH

and t

PHL

are the same as tpd.

1.5 V

1.5 V 1.5 V

1.5 V

1.5 V 1.5 V

Figure 3. Load Circuit and Voltage Waveforms

Page 9

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