Page 1
SN74ALVCH32501
36-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES144C – OCTOBER 1998 – REVISED MAY 2000
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Member of the Texas Instruments
Widebus
Family
D
EPIC
(Enhanced-Performance Implanted
CMOS) Submicron Process
D
UBT
(Universal Bus Transceiver)
Combines D-Type Latches and D-Type
Flip-Flops for Operation in Transparent,
Latched, or Clocked Mode
D
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D
Latch-Up Performance Exceeds 250 mA Per
JESD 17
D
Packaged in Plastic Fine-Pitch Ball Grid
Array Package
description
This 36-bit universal bus transceiver is designed for 1.65-V to 3.6-V VCC operation.
This device can be used as two 18-bit transceivers or one 36-bit transceiver. Data flow in each direction is
controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA), and clock (CLKAB and
CLKBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When
LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is low , the A data is stored
in the latch/flip-flop on the low-to-high transition of CLKAB. When OEAB is high, the outputs are active. When
OEAB is low , the outputs are in the high-impedance state.
Data flow for B to A is similar to that of A to B, but uses OEBA, LEBA, and CLKBA. The output enables are
complementary (OEAB is active high and OEBA is active low).
To ensure the high-impedance state during power up or power down, OEBA should be tied to VCC through a
pullup resistor and OEAB should be tied to GND through a pulldown resistor; the minimum value of the resistor
is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74ALVCH32501 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
†
INPUTS
OUTPUT
OEAB LEAB CLKAB A
B
L X X X Z
H HXLL
H HXHH
H L ↑ LL
H L ↑ HH
H LHXB
0
‡
H L L X
B
0
§
†
A-to-B data flow is shown; B-to-A flow is similar but
uses OEBA
, LEBA, and CLKBA.
‡
Output level before the indicated steady-state input
conditions were established, provided that CLKAB
was high before LEAB went low
§
Output level before the indicated steady-state input
conditions were established
Copyright 2000, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC, UBT, and Widebus are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Page 2
SN74ALVCH32501
36-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES144C – OCTOBER 1998 – REVISED MAY 2000
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
terminal assignments
123456
A 1A2
1A1 1LEAB 1CLKAB 1B1 1B2
B 1A4 1A3 1OEAB GND 1B3 1B4
C 1A6 1A5 GND GND 1B5 1B6
D 1A8 1A7 V
CC
V
CC
1B7 1B8
E 1A10 1A9 GND GND 1B9 1B10
F 1A12 1A11 GND GND 1B11 1B12
G 1A14 1A13 V
CC
V
CC
1B13 1B14
H 1A15 1A16 GND GND 1B16 1B15
J 1A17 1A18 1OEBA 1CLKBA 1B18 1B17
K NC 2LEAB 1LEBA GND 2CLKAB NC
L 2A2 2A1 2OEAB GND 2B1 2B2
M 2A4 2A3 GND GND 2B3 2B4
N 2A6 2A5 V
CC
V
CC
2B5 2B6
P 2A8 2A7 GND GND 2B7 2B8
R 2A10 2A9 GND GND 2B9 2B10
T 2A12 2A11 V
CC
V
CC
2B11 2B12
U 2A14 2A13 GND GND 2B13 2B14
V 2A15 2A16 2OEBA 2CLKBA 2B16 2B15
W 2A17 2A18 2LEBA GND 2B18 2B17
GKF PACKAGE
(TOP VIEW)
J
H
G
F
E
D
C
B
A
213465
P
N
M
L
K
T
R
U
W
V
NC – No internal connection
Page 3
SN74ALVCH32501
36-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES144C – OCTOBER 1998 – REVISED MAY 2000
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
1D
C1
CLK
1D
C1
CLK
1B1
1OEAB
1CLKAB
1LEAB
1LEBA
1CLKBA
1OEBA
1A1
B3
A4
A3
K3
J4
J3
A2
A5
To 17 Other Channels
Page 4
SN74ALVCH32501
36-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES144C – OCTOBER 1998 – REVISED MAY 2000
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
1D
C1
CLK
1D
C1
CLK
2B1
2OEAB
2CLKAB
2LEAB
2LEBA
2CLKBA
2OEBA
2A1
L3
K5
K2
W3
V4
V3
L2
L5
To 17 Other Channels
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, V
CC
–0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
: Except I/O ports (see Note 1) –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O ports (see Notes 1 and 2) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, VO (see Notes 1 and 2) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O
±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through each VCC or GND ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
JA
(see Note 3) 39°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output-current ratings are observed.
2. This value is limited to 4.6 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51.
Page 5
SN74ALVCH32501
36-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES144C – OCTOBER 1998 – REVISED MAY 2000
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions (see Note 4)
MIN MAX UNIT
V
CC
Supply voltage 1.65 3.6 V
VCC = 1.65 V to 1.95 V 0.65 × V
CC
V
IH
High-level input voltage
VCC = 2.3 V to 2.7 V
1.7
V
VCC = 2.7 V to 3.6 V 2
VCC = 1.65 V to 1.95 V 0.35 × V
CC
V
IL
Low-level input voltage
VCC = 2.3 V to 2.7 V
0.7
V
VCC = 2.7 V to 3.6 V 0.8
V
I
Input voltage 0 V
CC
V
V
O
Output voltage 0 V
CC
V
VCC = 1.65 V –4
p
VCC = 2.3 V –12
IOHHigh-level output current
VCC = 2.7 V –12
mA
VCC = 3 V –24
VCC = 1.65 V 4
p
VCC = 2.3 V 12
IOLLow-level output current
VCC = 2.7 V 12
mA
VCC = 3 V 24
∆t/∆v Input transition rise or fall rate 10 ns/V
T
A
Operating free-air temperature –40 85 °C
NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs
, literature number SCBA004.
Page 6
SN74ALVCH32501
36-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES144C – OCTOBER 1998 – REVISED MAY 2000
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS
V
CC
MIN TYP†MAX UNIT
IOH = –100 µA 1.65 V to 3.6 V VCC–0.2
IOH = –4 mA 1.65 V 1.2
IOH = –6 mA 2.3 V 2
V
OH
2.3 V 1.7
V
IOH = –12 mA
2.7 V 2.2
3 V 2.4
IOH = –24 mA 3 V 2
IOL = 100 µA 1.65 V to 3.6 V 0.2
IOL = 4 mA 1.65 V 0.45
IOL = 6 mA 2.3 V 0.4
V
OL
2.3 V 0.7
V
I
OL
= 12
mA
2.7 V 0.4
IOL = 24 mA 3 V 0.55
I
I
VI = VCC or GND 3.6 V ±5 µA
VI = 0.58 V
25
VI = 1.07 V
1.65 V
–25
VI = 0.7 V
45
I
I(hold)
VI = 1.7 V
2.3 V
–45
µA
()
VI = 0.8 V
75
VI = 2 V
3 V
–75
VI = 0 to 3.6 V
‡
3.6 V ±500
I
OZ
§
VO = VCC or GND 3.6 V ±10 µA
I
CC
VI = VCC or GND, IO = 0 3.6 V 20 µA
∆I
CC
One input at VCC – 0.6 V, Other inputs at VCC or GND 3 V to 3.6 V 750 µA
C
i
Control inputs VI = VCC or GND 3.3 V 4 pF
C
io
A or B ports VO = VCC or GND 3.3 V 8 pF
†
All typical values are at VCC = 3.3 V, TA = 25°C.
‡
This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.
§
For I/O ports, the parameter IOZ includes the input leakage current.
Page 7
SN74ALVCH32501
36-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES144C – OCTOBER 1998 – REVISED MAY 2000
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figures 1 through 3)
VCC = 1.8 V
VCC = 2.5 V
± 0.2 V
VCC = 2.7 V
VCC = 3.3 V
± 0.3 V
UNIT
MIN MAX MIN MAX MIN MAX MIN MAX
f
clock
Clock frequency
†
150 150 150 MHz
Pulse
LE high
†
3.3 3.3 3.3
t
w
duration
CLK high or low
†
3.3 3.3 3.3
ns
Data before CLK↑
†
2.2 2.1 1.7
t
su
Setup time
CLK high
†
1.9 1.6 1.5
ns
Data before LE↓
CLK low
†
1.3 1.1 1
Data after CLK↑
†
0.6 0.6 0.7
thHold time
Data after LE↓ CLK high or low
†
1.4 1.7 1.4
ns
†
This information was not available at the time of publication.
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 1 through 3)
PARAMETER
FROM
TO
VCC = 1.8 V
VCC = 2.5 V
± 0.2 V
VCC = 2.7 V
VCC = 3.3 V
± 0.3 V
UNIT
(INPUT)
(OUTPUT)
MIN TYP MIN MAX MIN MAX MIN MAX
f
max
†
150 150 150 MHz
A or B B or A
†
1 4.8 4.5 1 3.9
t
pd
LE
†
1.1 5.7 5.3 1.3 4.6
ns
CLK
A or B
†
1.2 6.1 5.6 1.4 4.9
t
en
OEAB B
†
1 5.8 5.3 1 4.6 ns
t
dis
OEAB B
†
1.5 6.2 5.7 1.4 5 ns
t
en
OEBA A
†
1.3 6.3 6 1.1 5 ns
t
dis
OEBA A
†
1.3 5.3 4.6 1.3 4.2 ns
†
This information was not available at the time of publication.
operating characteristics, T
A
= 25°C
VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V
PARAMETER
TEST CONDITIONS
TYP TYP TYP
UNIT
Power dissipation
Outputs enabled
†
44 54
p
C
pd
capacitance
Outputs disabled
C
L
=
0
,f = 10 MHz
†
6 6
pF
†
This information was not available at the time of publication.
Page 8
SN74ALVCH32501
36-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES144C – OCTOBER 1998 – REVISED MAY 2000
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
V
CC
= 1.8 V
VCC/2
VCC/2
VCC/2VCC/2
VCC/2VCC/2
VCC/2
VCC/2
V
OH
V
OL
t
h
t
su
From Output
Under Test
CL = 30 pF
(see Note A)
LOAD CIRCUIT
S1
Open
GND
1 kΩ
1 kΩ
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2 × V
CC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
t
PZL
t
PZH
t
PLZ
t
PHZ
0 V
VOL + 0.15 V
VOH – 0.15 V
0 V
V
CC
0 V
0 V
t
w
V
CC
V
CC
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
Timing
Input
Data
Input
Input
t
pd
t
PLZ/tPZL
t
PHZ/tPZH
Open
2 × V
CC
GND
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. t
PLZ
and t
PHZ
are the same as t
dis
.
F. t
PZL
and t
PZH
are the same as ten.
G. t
PLH
and t
PHL
are the same as tpd.
0 V
V
CC
VCC/2
t
PHL
VCC/2 VCC/2
V
CC
0 V
V
OH
V
OL
Input
Output
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VCC/2 VCC/2
t
PLH
2 × V
CC
V
CC
Figure 1. Load Circuit and Voltage Waveforms
Page 9
SN74ALVCH32501
36-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES144C – OCTOBER 1998 – REVISED MAY 2000
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
V
CC
= 2.5 V ± 0.2 V
VCC/2
VCC/2
VCC/2VCC/2
VCC/2VCC/2
VCC/2
VCC/2
V
OH
V
OL
t
h
t
su
From Output
Under Test
CL = 30 pF
(see Note A)
LOAD CIRCUIT
S1
Open
GND
500 Ω
500 Ω
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2 × V
CC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
t
PZL
t
PZH
t
PLZ
t
PHZ
0 V
VOL + 0.15 V
VOH – 0.15 V
0 V
V
CC
0 V
0 V
t
w
V
CC
V
CC
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
Timing
Input
Data
Input
Input
t
pd
t
PLZ/tPZL
t
PHZ/tPZH
Open
2 × V
CC
GND
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. t
PLZ
and t
PHZ
are the same as t
dis
.
F. t
PZL
and t
PZH
are the same as ten.
G. t
PLH
and t
PHL
are the same as tpd.
0 V
V
CC
VCC/2
t
PHL
VCC/2 VCC/2
V
CC
0 V
V
OH
V
OL
Input
Output
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VCC/2 VCC/2
t
PLH
2 × V
CC
V
CC
Figure 2. Load Circuit and Voltage Waveforms
Page 10
SN74ALVCH32501
36-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES144C – OCTOBER 1998 – REVISED MAY 2000
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
V
CC
= 2.7 V AND 3.3 V ± 0.3 V
t
PLZ
t
PHZ
V
OH
V
OL
t
h
t
su
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1
6 V
Open
GND
500 Ω
500 Ω
t
PLH
t
PHL
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 6 V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
t
PZL
t
PZH
1.5 V
1.5 V
1.5 V 1.5 V
2.7 V
0 V
1.5 V 1.5 V
V
OH
V
OL
0 V
1.5 V
VOL + 0.3 V
1.5 V
VOH – 0.3 V
0 V
1.5 V
2.7 V
0 V
1.5 V 1.5 V
0 V
2.7 V
0 V
1.5 V 1.5 V
t
w
Input
2.7 V
2.7 V
3 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
Timing
Input
Data
Input
Output
Input
t
pd
t
PLZ/tPZL
t
PHZ/tPZH
Open
6 V
GND
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. t
PLZ
and t
PHZ
are the same as t
dis
.
F. t
PZL
and t
PZH
are the same as ten.
G. t
PLH
and t
PHL
are the same as tpd.
Figure 3. Load Circuit and Voltage Waveforms
Page 11
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any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
Customers are responsible for their applications using TI components.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
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Copyright 2000, Texas Instruments Incorporated
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