Datasheet SN74ALVCH32245KR Datasheet (Texas Instruments)

Page 1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SN74AL VCH32245

32-BIT BUS TRANSCEIVER

WITH 3-STATE OUTPUTS

SCES282 – OCTOBER 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Member of the Texas Instruments

Widebus+

 Family

EPIC

 (Enhanced-Performance Implanted

CMOS) Submicron Process

Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors

Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II

ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101)

Packaged in Plastic Fine-Pitch Ball Grid Array Package

description

This 32-bit noninverting bus transceiver is designed for 1.65-V to 3.6-V VCC operation. The SN74ALVCH32245 is designed for asynchronous communication between data buses. The

control-function implementation minimizes external timing requirements. This device can be used as four 8-bit transceivers, two 16-bit transceivers, or one 32-bit transceiver. It allows

data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so that the buses are effectively isolated.

T o ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. The SN74ALVCH32245 is characterized for operation from –40°C to 85°C.

FUNCTION TABLE

(each 8-bit section)

INPUTS

OE DIR

OPERATION

L L B data to A bus L H A data to B bus H X Isolation

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

EPIC and Widebus+ are trademarks of Texas Instruments Incorporated.

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SN74ALVCH32245 32-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS

SCES282 – OCTOBER 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

terminal assignments

1 2 3 4 5 6

A 1B2 1B1 1DIR 1OE 1A1 1A2 B 1B4 1B3 GND GND 1A3 1A4 C 1B6 1B5 V

1A5 1A6

D 1B8 1B7 GND GND 1A7 1A8 E 2B2 2B1 GND GND 2A1 2A2 F 2B4 2B3 V

2A3 2A4

G 2B6 2B5 GND GND 2A5 2A6 H 2B8 2B7 2DIR 2OE 2A7 2A8 J 3B2 3B1 3DIR 3OE 3A1 3A2 K 3B4 3B3 GND GND 3A3 3A4 L 3B6 3B5 V

3A5 3A6

M 3B8 3B7 GND GND 3A7 3A8 N 4B2 4B1 GND GND 4A1 4A2 P 4B4 4B3 V

4A3 4A4

R 4B6 4B5 GND GND 4A5 4A6 T 4B7 4B8 4DIR 4OE 4A8 4A7

logic diagram (positive logic)

To Seven Other Channels

1DIR

1A1

1B1

1OE

To Seven Other Channels

2DIR

2A1

2B1

2OE

To Seven Other Channels

3DIR

3A1

3B1

3OE

To Seven Other Channels

4DIR

4A1

4B1

4OE

GKE PACKAGE

(TOP VIEW)

A B C D E

F G H

L M N

123456

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SN74ALVCH32245

32-BIT BUS TRANSCEIVER

WITH 3-STATE OUTPUTS

SCES282 – OCTOBER 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

†

Supply voltage range, VCC –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, VI: Except I/O ports (see Note 1) –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I/O ports (see Notes 1 and 2) –0.5 V to V

+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . .

Output-voltage range, VO (see Notes 1 and 2) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input clamp current, IIK (VI < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output clamp current, IOK (VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous output current, IO ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous current through each V

or GND ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Package thermal impedance, θ

(see Note 3) 40°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.

2. This value is limited to 4.6 V maximum.

3. The package thermal impedance is calculated in accordance with JESD 51.

recommended operating conditions (see Note 4)

MIN MAX UNIT

Supply voltage 1.65 3.6 V

VCC = 1.65 V to 1.95 V 0.65 × V

High-level input voltage

VCC = 2.3 V to 2.7 V

1.7

V VCC = 2.7 V to 3.6 V 2 VCC = 1.65 V to 1.95 V 0.35 × V

Low-level input voltage

VCC = 2.3 V to 2.7 V

0.7

V VCC = 2.7 V to 3.6 V 0.8

Input voltage 0 V

Output voltage 0 V

V VCC = 1.65 V –4

VCC = 2.3 V –8

IOHHigh-level output current

VCC = 2.7 V –12

VCC = 3 V –24 VCC = 1.65 V 4

VCC = 2.3 V 8

IOLLow-level output current

VCC = 2.7 V 12

VCC = 3 V 24

∆t/∆v Input transition rise or fall rate 10 ns/V T

Operating free-air temperature –40 85 °C

NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,

Implications of Slow or Floating CMOS Inputs

, literature number SCBA004.

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SN74ALVCH32245 32-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS

SCES282 – OCTOBER 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS

MIN TYP†MAX UNIT

IOH = –100 µA 1.65 V to 3.6 V VCC–0.2 IOH = –4 mA 1.65 V 1.2 IOH = –8 mA 2.3 V 1.7

2.7 V 2.2

= –12

3 V 2.4 IOH = –24 mA 3 V 2.2 IOL = 100 µA 1.65 V to 3.6 V 0.2 IOL = 4 mA 1.65 V 0.45

IOL = 8 mA 2.3 V 0.7

V IOL = 12 mA 2.7 V 0.4 IOL = 24 mA 3 V 0.55

VI = VCC or GND 3.6 V ±5 µA VI = 0.58 V 1.65 V 25 VI = 1.07 V 1.65 V –25 VI = 0.7 V 2.3 V 45

I(hold)

VI = 1.7 V 2.3 V –45

µA

()

VI = 0.8 V 3 V 75 VI = 2 V 3 V –75 VI = 0 to 3.6 V

‡

3.6 V ±500

VO = VCC or GND 3.6 V ±10 µA

VI = VCC or GND, IO = 0 3.6 V 40 µA

∆I

One input at VCC – 0.6 V, Other inputs at VCC or GND 3 V to 3.6 V 750 µA

Control inputs VI = VCC or GND 3.3 V 4 pF

A or B ports VO = VCC or GND 3.3 V 8 pF

†

All typical values are at VCC = 3.3 V, TA = 25°C.

‡

This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.

For I/O ports, the parameter IOZ includes the input leakage current.

switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 3)

PARAMETER

FROM

VCC = 1.8 V

± 0.15 V

VCC = 2.5 V

± 0.2 V

VCC = 2.7 V

VCC = 3.3 V

± 0.3 V

UNIT

(INPUT)

(OUTPUT)

MIN MAX MIN MAX MIN MAX MIN MAX

A or B B or A

¶ ¶

1 3.7 3.6 1 3 ns

A or B

¶ ¶

1 5.7 5.4 1 4.4 ns

dis

A or B

¶ ¶

1 5.2 4.6 1 4.1 ns

This information was not available at the time of publication.

operating characteristics, T

= 25° C

VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V

PARAMETER

TEST CONDITIONS

TYP TYP TYP

UNIT

Power dissipation

Outputs enabled

22 29

capacitance

Outputs disabled

= 50 pF,f = 10 MHz

4 5

This information was not available at the time of publication.

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SN74ALVCH32245

32-BIT BUS TRANSCEIVER

WITH 3-STATE OUTPUTS

SCES282 – OCTOBER 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

= 1.8 V ± 0.15 V

VCC/2

VCC/2VCC/2

From Output

Under Test

CL = 30 pF

(see Note A)

LOAD CIRCUIT

Open

GND

1 kΩ

Output

Control (low-level enabling)

Output

Waveform 1

S1 at 2 × V

(see Note B)

Output

Waveform 2

S1 at GND

(see Note B)

PZL

PZH

PLZ

PHZ

0 V

VOL + 0.15 V

VOH – 0.15 V

0 V

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

VOLTAGE WAVEFORMS

PULSE DURATION

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

Timing

Input

Data

Input

PLZ/tPZL

PHZ/tPZH

Open

2 × V

GND

TEST S1

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. t

PLZ

and t

PHZ

are the same as t

dis

F. t

PZL

and t

PZH

are the same as ten.

G. t

PLH

and t

PHL

are the same as tpd.

0 V

VCC/2

PHL

VCC/2 VCC/2

0 V

Input

Output

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

VCC/2 VCC/2

PLH

2 × V

Figure 1. Load Circuit and Voltage Waveforms

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SN74ALVCH32245 32-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS

SCES282 – OCTOBER 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

= 2.5 V ± 0.2 V

VCC/2

VCC/2VCC/2

From Output

Under Test

CL = 30 pF

(see Note A)

LOAD CIRCUIT

Open

GND

500 Ω

Output

Control

(low-level

enabling)

Output

Waveform 1

S1 at 2 × V

(see Note B)

Output

Waveform 2

S1 at GND

(see Note B)

PZL

PZH

PLZ

PHZ

0 V

VOL + 0.15 V

VOH – 0.15 V

0 V

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

VOLTAGE WAVEFORMS

PULSE DURATION

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

Timing

Input

Data

Input

PLZ/tPZL

PHZ/tPZH

Open

2 × V

GND

TEST S1

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr≤ 2 ns, tf≤ 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. t

PLZ

and t

PHZ

are the same as t

dis

F. t

PZL

and t

PZH

are the same as ten.

G. t

PLH

and t

PHL

are the same as tpd.

0 V

VCC/2

PHL

VCC/2 VCC/2

0 V

Input

Output

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

VCC/2 VCC/2

PLH

2 × V

Figure 2. Load Circuit and Voltage Waveforms

Page 7

SN74ALVCH32245

32-BIT BUS TRANSCEIVER

WITH 3-STATE OUTPUTS

SCES282 – OCTOBER 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

= 2.7 V AND 3.3 V ± 0.3 V

PZL

PZH

From Output

Under Test

CL = 50 pF

(see Note A)

LOAD CIRCUIT

6 V

Open

GND

500 Ω

PLH

PHL

Output

Control

(low-level

enabling)

Output

Waveform 1

S1 at 6 V

(see Note B)

Output

Waveform 2

S1 at GND

(see Note B)

PLZ

PHZ

2.7 V

0 V

VOL + 0.3 V

VOH – 0.3 V

0 V

2.7 V

0 V

2.7 V

0 V

Input

2.7 V

3 V

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

VOLTAGE WAVEFORMS

PULSE DURATION

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

Timing

Input

Data

Input

Output

Input

PLZ/tPZL

PHZ/tPZH

Open

6 V

GND

TEST S1

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤2.5 ns, tf ≤2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. t

PLZ

and t

PHZ

are the same as t

dis

F. t

PZL

and t

PZH

are the same as ten.

G. t

PLH

and t

PHL

are the same as tpd.

1.5 V

1.5 V 1.5 V

1.5 V

1.5 V 1.5 V

Figure 3. Load Circuit and Voltage Waveforms

Page 8

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