Datasheet SN74ALVCH32244KR Datasheet (Texas Instruments)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SN74AL VCH32244

32-BIT BUFFER/DRIVER

WITH 3-STATE OUTPUTS

SCES281 – OCTOBER 1999

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D

Member of the Texas Instruments

Widebus+

 Family

D

EPIC

 (Enhanced-Performance Implanted

CMOS) Submicron Process

D

Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors

D

Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II

D

ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)

D

Packaged in Plastic Fine-Pitch Ball Grid
Array Package

description

This 32-bit buffer/driver is designed for 1.65-V to 3.6-V VCC operation.
The SN74ALVCH32244 is designed specifically to improve the performance and density of 3-state memory

address drivers, clock drivers, and bus-oriented receivers and transmitters.
The device can be used as eight 4-bit buffers, four 8-bit buffers, two 16-bit buffers, or one 32-bit buffer . It provides

true outputs and symmetrical active-low output-enable (OE) inputs.
T o ensure the high-impedance state during power up or power down, OE

should be tied to VCC through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74ALVCH32244 is characterized for operation from –40°C to 85°C.

FUNCTION TABLE

(each 4-bit buffer)

INPUTS

OUTPUT

OE A

Y

L H H
L LL
H X Z

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

Copyright  1999, Texas Instruments Incorporated

EPIC and Widebus+ are trademarks of Texas Instruments Incorporated.

SN74ALVCH32244
32-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS

SCES281 – OCTOBER 1999

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

terminal assignments

1 2 3 4 5 6

A 1Y2 1Y1 1OE 2OE 1A1 1A2
B 1Y4 1Y3 GND GND 1A3 1A4
C 2Y2 2Y1 V

CC

V

CC

2A1 2A2

D 2Y4 2Y3 GND GND 2A3 2A4
E 3Y2 3Y1 GND GND 3A1 3A2
F 3Y4 3Y3 V

CC

V

CC

3A3 3A4

G 4Y2 4Y1 GND GND 4A1 4A2
H 4Y4 4Y3 4OE 3OE 4A3 4A4
J 5Y2 5Y1 5OE 6OE 5A1 5A2
K 5Y4 5Y3 GND GND 5A3 5A4
L 6Y2 6Y1 V

CC

V

CC

6A1 6A2

M 6Y4 6Y3 GND GND 6A3 6A4
N 7Y2 7Y1 GND GND 7A1 7A2
P 7Y4 7Y3 V

CC

V

CC

7A3 7A4

R 8Y2 8Y1 GND GND 8A1 8A2
T 8Y3 8Y4 8OE 7OE 8A4 8A3

GKE PACKAGE

(TOP VIEW)

A
B
C
D
E

F
G
H

J

K

L
M
N

P

R

T

123456

SN74ALVCH32244

32-BIT BUFFER/DRIVER

WITH 3-STATE OUTPUTS

SCES281 – OCTOBER 1999

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

logic diagram (positive logic)

1OE

1A1

1A2

1A3

1A4

1Y1

1Y2

1Y3

1Y4

A3

A5

A6

B5

B6

A2

A1

B2

B1

2OE

2A1

2A2

2A3

2A4

2Y1

2Y2

2Y3

2Y4

A4

C5

C6

D5

D6

C2

C1

D2

D1

3OE

3A1

3A2

3A3

3A4

3Y1

3Y2

3Y3

3Y4

H4

E5

E6

F5

F6

E2

E1

F2

F1

4OE

4A1

4A2

4A3

4A4

4Y1

4Y2

4Y3

4Y4

H3

G5

G6

H6

H5

G2

G1

H1

H2

5OE

5A1

5A2

5A3

5A4

5Y1

5Y2

5Y3

5Y4

J3

J5

J6

K5

K6

J2

J1

K2

K1

6OE

6A1

6A2

6A3

6A4

6Y1

6Y2

6Y3

6Y4

J4

L5

L6

M5

M6

L2

L1

M2

M1

7OE

7A1

7A2

7A3

7A4

7Y1

7Y2

7Y3

7Y4

T4

N5

N6

P5

P6

N2

N1

P2

P1

8OE

8A1

8A2

8A3

8A4

8Y1

8Y2

8Y3

8Y4

T3

R5

R6

T6

T5

R2

R1

T1

T2

SN74ALVCH32244
32-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS

SCES281 – OCTOBER 1999

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

†

Supply voltage range, VCC –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, VI (see Note 1) –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output voltage range, V

O

(see Notes 1 and 2) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input clamp current, IIK (VI < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output clamp current, IOK (VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous output current, IO ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous current through each VCC or GND ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Package thermal impedance, θ

JA

(see Note 3) 40°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.

2. This value is limited to 4.6 V maximum.

3. The package thermal impedance is calculated in accordance with JESD 51.

recommended operating conditions (see Note 4)

MIN MAX UNIT

pp

Operating 1.65 3.6

VCCSuppl

y v

oltage

Data retention only 1.5

V

VCC = 1.65 V to 1.95 V 0.65 × V

CC

V

IH

High-level input voltage

VCC = 2.3 V to 2.7 V

1.7

V
VCC = 2.7 V to 3.6 V 2
VCC = 1.65 V to 1.95 V 0.35 × V

CC

V

IL

Low-level input voltage

VCC = 2.3 V to 2.7 V

0.7

V
VCC = 2.7 V to 3.6 V 0.8

V

I

Input voltage 0 V

CC

V

V

O

Output voltage 0 V

CC

V
VCC = 1.65 V –4

p

VCC = 2.3 V –8

IOHHigh-level output current

VCC = 2.7 V –12

mA

VCC = 3 V –24
VCC = 1.65 V 4

p

VCC = 2.3 V 8

IOLLow-level output current

VCC = 2.7 V 12

mA

VCC = 3 V 24

∆t/∆v Input transition rise or fall rate 10 ns/V
T

A

Operating free-air temperature –40 85 °C

NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,

Implications of Slow or Floating CMOS Inputs

, literature number SCBA004.

SN74ALVCH32244

32-BIT BUFFER/DRIVER

WITH 3-STATE OUTPUTS

SCES281 – OCTOBER 1999

5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)

PARAMETER TEST CONDITIONS

V

CC

MIN TYP†MAX UNIT

IOH = –100 µA 1.65 V to 3.6 V VCC–0.2
IOH = –4 mA 1.65 V 1.2
IOH = –8 mA 2.3 V 1.7

V

OH

2.7 V 2.2

V

I

OH

= –12

mA

3 V 2.4
IOH = –24 mA 3 V 2.2
IOL = 100 µA 1.65 V to 3.6 V 0.2
IOL = 4 mA 1.65 V 0.45

V

OL

IOL = 8 mA 2.3 V 0.7

V
IOL = 12 mA 2.7 V 0.4
IOL = 24 mA 3 V 0.55

I

I

VI = VCC or GND 3.6 V ±5 µA
VI = 0.58 V 1.65 V 25
VI = 1.07 V 1.65 V –25
VI = 0.7 V 2.3 V 45

I

I(hold)

VI = 1.7 V 2.3 V –45

µA

()

VI = 0.8 V 3 V 75
VI = 2 V 3 V –75
VI = 0 to 3.6 V

‡

3.6 V ±500

I

OZ

VO = VCC or GND 3.6 V ±10 µA

I

CC

VI = VCC or GND, IO = 0 3.6 V 40 µA

∆I

CC

One input at VCC – 0.6 V, Other inputs at VCC or GND 3 V to 3.6 V 750 µA

Control inputs

3

p

C

i

Data inputs

V

I

=

V

CC

or GND

3.3 V

6

pF

C

o

Outputs VO = VCC or GND 3.3 V 7 pF

†

All typical values are at VCC = 3.3 V, TA = 25°C.

‡

This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.

switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 1 through 3)

PARAMETER

FROM

TO

VCC = 1.8 V

± 0.15 V

VCC = 2.5 V

± 0.2 V

VCC = 2.7 V

VCC = 3.3 V

± 0.3 V

UNIT

(INPUT)

(OUTPUT)

MIN MAX MIN MAX MIN MAX MIN MAX

t

pd

A Y

§ §

1 3.7 3.6 1 3 ns

t

en

OE

Y

§ §

1 5.7 5.4 1 4.4 ns

t

dis

OE

Y

§ §

1 5.2 4.6 1 4.1 ns

§

This information was not available at the time of publication.

operating characteristics, T

A

= 25°C

VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V

PARAMETER

TEST CONDITIONS

TYP TYP TYP

UNIT

p

p

Outputs enabled

§

16 19

p

CpdPower dissipation capacitance

Outputs disabled

C

L

= 0,f = 10 MHz

§

4 5

pF

§

This information was not available at the time of publication.

SN74ALVCH32244
32-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS

SCES281 – OCTOBER 1999

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

V

CC

= 1.8 V ± 0.15 V

VCC/2

VCC/2

VCC/2VCC/2

VCC/2VCC/2

VCC/2VCC/2

V

OH

V

OL

t

h

t

su

From Output

Under Test

CL = 30 pF

(see Note A)

LOAD CIRCUIT

S1

Open

GND

1 kΩ

1 kΩ

Output

Control
(low-level
enabling)

Output

Waveform 1

S1 at 2 × V

CC

(see Note B)

Output

Waveform 2

S1 at GND

(see Note B)

t

PZL

t

PZH

t

PLZ

t

PHZ

0 V

VOL + 0.15 V

VOH – 0.15 V

0 V

V

CC

0 V

0 V

t

w

V

CC

V

CC

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

VOLTAGE WAVEFORMS

PULSE DURATION

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

Timing

Input

Data

Input

Input

t

pd

t

PLZ/tPZL

t

PHZ/tPZH

Open

2 × V

CC

GND

TEST S1

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. t

PLZ

and t

PHZ

are the same as t

dis

.

F. t

PZL

and t

PZH

are the same as ten.

G. t

PLH

and t

PHL

are the same as tpd.

0 V

V

CC

VCC/2

t

PHL

VCC/2 VCC/2

V

CC

0 V

V

OH

V

OL

Input

Output

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

VCC/2 VCC/2

t

PLH

2 × V

CC

V

CC

Figure 1. Load Circuit and Voltage Waveforms

SN74ALVCH32244

32-BIT BUFFER/DRIVER

WITH 3-STATE OUTPUTS

SCES281 – OCTOBER 1999

7

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

V

CC

= 2.5 V ± 0.2 V

VCC/2

VCC/2

VCC/2VCC/2

VCC/2VCC/2

VCC/2VCC/2

V

OH

V

OL

t

h

t

su

From Output

Under Test

CL = 30 pF

(see Note A)

LOAD CIRCUIT

S1

Open

GND

500 Ω

500 Ω

Output

Control

(low-level

enabling)

Output

Waveform 1

S1 at 2 × V

CC

(see Note B)

Output

Waveform 2

S1 at GND

(see Note B)

t

PZL

t

PZH

t

PLZ

t

PHZ

0 V

VOL + 0.15 V

VOH – 0.15 V

0 V

V

CC

0 V

0 V

t

w

V

CC

V

CC

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

VOLTAGE WAVEFORMS

PULSE DURATION

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

Timing

Input

Data

Input

Input

t

pd

t

PLZ/tPZL

t

PHZ/tPZH

Open

2 × V

CC

GND

TEST S1

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr≤ 2 ns, tf≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.

E. t

PLZ

and t

PHZ

are the same as t

dis

.

F. t

PZL

and t

PZH

are the same as ten.

G. t

PLH

and t

PHL

are the same as tpd.

0 V

V

CC

VCC/2

t

PHL

VCC/2 VCC/2

V

CC

0 V

V

OH

V

OL

Input

Output

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

VCC/2 VCC/2

t

PLH

2 × V

CC

V

CC

Figure 2. Load Circuit and Voltage Waveforms

SN74ALVCH32244
32-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS

SCES281 – OCTOBER 1999

8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

V

CC

= 2.7 V AND 3.3 V ± 0.3 V

t

PZL

t

PZH

V

OH

V

OL

t

h

t

su

From Output

Under Test

CL = 50 pF

(see Note A)

LOAD CIRCUIT

S1

6 V

Open

GND

500 Ω

500 Ω

t

PLH

t

PHL

Output

Control

(low-level

enabling)

Output

Waveform 1

S1 at 6 V

(see Note B)

Output

Waveform 2

S1 at GND

(see Note B)

t

PLZ

t

PHZ

2.7 V

0 V

V

OH

V

OL

0 V

VOL + 0.3 V

VOH – 0.3 V

0 V

2.7 V

0 V

0 V

2.7 V

0 V

t

w

Input

2.7 V

2.7 V

3 V

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

VOLTAGE WAVEFORMS

PULSE DURATION

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

Timing

Input

Data

Input

Output

Input

t

pd

t

PLZ/tPZL

t

PHZ/tPZH

Open

6 V

GND

TEST S1

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤2.5 ns, tf ≤2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. t

PLZ

and t

PHZ

are the same as t

dis

.

F. t

PZL

and t

PZH

are the same as ten.

G. t

PLH

and t

PHL

are the same as tpd.

1.5 V

1.5 V 1.5 V

1.5 V 1.5 V

1.5 V 1.5 V

1.5 V

1.5 V

1.5 V 1.5 V

1.5 V 1.5 V

Figure 3. Load Circuit and Voltage Waveforms

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any product or service without notice, and advise customers to obtain the latest version of relevant information
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pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.

CERT AIN APPLICATIONS USING SEMICONDUCT OR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
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BE FULLY AT THE CUSTOMER’S RISK.

In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
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Copyright  1999, Texas Instruments Incorporated