Datasheet SN74ALVCH245DGVR, SN74ALVCH245DW, SN74ALVCH245DWR, SN74ALVCH245PWR Datasheet (Texas Instruments)

OPERATION

SN74ALVCH245

OCTAL BUS TRANSCEIVER

WITH 3-STATE OUTPUTS

SCES119D – JULY 1997 – REVISED MAY 1999

D

EPIC

 (Enhanced-Performance Implanted

CMOS) Submicron Process

D

Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II

D

Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors

D

Package Options Include Plastic
Small-Outline (DW), Thin Very
Small-Outline (DGV), and Thin Shrink
Small-Outline (PW) Packages

DGV, DW, OR PW PACKAGE

DIR

A1
A2
A3
A4
A5
A6
A7
A8

GND

(TOP VIEW)

1

20

2

19

3

18

4

17

5

16

6

15

7

14

8

13

9

12

10

11

V
OE
B1
B2
B3
B4
B5
B6
B7
B8

CC

description

This octal bus transceiver is designed for 1.65-V to 3.6-V VCC operation.
The SN74AL VCH245 is designed for asynchronous communication between data buses. The device transmits

data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the
direction-control (DIR) input. The output-enable (OE
effectively isolated.

T o ensure the high-impedance state during power up or power down, OE
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

) input can be used to disable the device so the buses are

should be tied to VCC through a pullup

The SN74ALVCH245 is characterized for operation from –40°C to 85°C.

FUNCTION TABLE

INPUTS

OE DIR

L L B data to A bus
L H A data to B bus

H X Isolation

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  1999, Texas Instruments Incorporated

1

SN74ALVCH245
OCTAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS

SCES119D – JULY 1997 – REVISED MAY 1999

logic symbol

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

†

OE

DIR

A1

A2
A3
A4
A5
A6
A7
A8

19
1

2

3
4
5
6
7
8
9

G3
3 EN1 [BA]

3 EN2 [AB]

1

2

logic diagram (positive logic)

1

DIR

18

17
16
15
14
13
12
11

B1

B2
B3
B4
B5
B6
B7
B8

A1

19

OE

2

18

B1

To Seven Other Channels

2

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IOHHigh-level output current

mA

IOLLow-level output current

mA

SN74ALVCH245

OCTAL BUS TRANSCEIVER

WITH 3-STATE OUTPUTS

SCES119D – JULY 1997 – REVISED MAY 1999

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V
Input voltage range, V

Output voltage range, V
Input clamp current, I
Output clamp current, I
Continuous output current, I
Continuous current through V
Package thermal impedance, θ

–0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC

: Except I/O ports (see Note 1) –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I

I/O ports (see Notes 1 and 2) –0.5 V to V

(see Notes 1 and 2) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

O

(VI < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

IK

(VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

OK

±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

O

or GND ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC

(see Note 3): DGV package 146°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

JA

CC

†

+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . .

DW package 97°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PW package 128°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.

2. This value is limited to 4.6 V maximum.

3. The package thermal impedance is calculated in accordance with JESD 51.

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

recommended operating conditions (see Note 4)

MIN MAX UNIT

V

V

V

V
V

∆t/∆v Input transition rise or fall rate 10 ns/V
T

NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,

Supply voltage 1.65 3.6 V

CC

VCC = 1.65 V to 1.95 V 0.65 × V

High-level input voltage

IH

Low-level input voltage

IL

Input voltage 0 V

I

Output voltage 0 V

O

p

p

Operating free-air temperature –40 85 °C

A

Implications of Slow or Floating CMOS Inputs

, literature number SCBA004.

VCC = 2.3 V to 2.7 V 1.7
VCC = 2.7 V to 3.6 V 2
VCC = 1.65 V to 1.95 V 0.35 × V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V 0.8

VCC = 1.65 V –4
VCC = 2.3 V –12
VCC = 2.7 V –12
VCC = 3 V –24
VCC = 1.65 V 4
VCC = 2.3 V 12
VCC = 2.7 V 12
VCC = 3 V 24

CC

0.7

CC
CC

V

CC

V

V
V

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3

SN74ALVCH245

V

V

I

mA

()

(INPUT)

(OUTPUT)

PARAMETER

UNIT

C

L

,

pF

OCTAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS

SCES119D – JULY 1997 – REVISED MAY 1999

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)

PARAMETER TEST CONDITIONS

IOH = –100 µA 1.65 V to 3.6 V VCC–0.2
IOH = –4 mA 1.65 V 1.2
IOH = –6 mA 2.3 V 2

V

OH

IOH = –12 mA

IOH = –24 mA 3 V 2
IOL = 100 µA 1.65 V to 3.6 V 0.2
IOL = 4 mA 1.65 V 0.45

OL

I

I

I

I(hold)

§

I

OZ

I

CC

∆I

CC

C
C

†

All typical values are at VCC = 3.3 V, TA = 25°C.

‡

This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.

§

For I/O ports, the parameter IOZ includes the input leakage current.

Control inputs VI = VCC or GND 3.3 V 4.5 pF

i

A or B ports VO = VCC or GND 3.3 V 12 pF

io

IOL = 6 mA 2.3 V 0.4

= 12

OL

IOL = 24 mA 3 V 0.55
VI = VCC or GND 3.6 V ±5 µA
VI = 0.58 V 1.65 V 25
VI = 1.07 V 1.65 V –25
VI = 0.7 V 2.3 V 45
VI = 1.7 V 2.3 V –45
VI = 0.8 V 3 V 75
VI = 2 V 3 V –75
VI = 0 to 3.6 V
VO = VCC or GND, 3.6 V ±10 µA
VI = VCC or GND, IO = 0 3.6 V 10 µA
One input at VCC – 0.6 V, Other inputs at VCC or GND 3 V to 3.6 V 750 µA

‡

V

CC

2.3 V 1.7

2.7 V 2.2
3 V 2.4

2.3 V 0.7

2.7 V 0.4

3.6 V ±500

MIN TYP†MAX UNIT

V

µA

switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 1 through 3)

PARAMETER

t

pd

t

en

t

dis

FROM

A or B

operating characteristics, T

Power dissipation capacitance

pd

per transceiver

4

OE
OE

TO

B or A
A or B

A or B

= 25°C

A

Outputs enabled
Outputs disabled

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VCC = 1.8 V

± 0.15 V

MIN MAX MIN MAX MIN MAX MIN MAX

1.5 6 1 3.5 3.6 1.3 3.4 ns

3.4 8.6 2 6 6.3 1.6 5.5 ns

2.7 8 1 4.8 5.3 1.7 5.5 ns

TEST

CONDITIONS

C

f = 10 MHz

= 0,

VCC = 2.5 V

± 0.2 V

VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V

VCC = 2.7 V

TYP TYP TYP

25 28 31

0 0 0

VCC = 3.3 V

± 0.3 V

UNIT

p

From Output

Under Test

CL = 30 pF

(see Note A)

OCTAL BUS TRANSCEIVER

SCES119D – JULY 1997 – REVISED MAY 1999

PARAMETER MEASUREMENT INFORMATION

= 1.8 V ± 0.15 V

V

CC

2 × V

Open

GND

CC

TEST S1

t

pd

t

PLZ/tPZL

t

PHZ/tPZH

1 kΩ

1 kΩ

S1

SN74ALVCH245

WITH 3-STATE OUTPUTS

Open

2 × V

CC

GND

LOAD CIRCUIT

Timing

Input

t

su

Data

Input

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

Input

t

PLH

Output

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. t

F. t

G. t

VCC/2 VCC/2

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

and t

PLZ
PZL
PLH

and t

and t

PHZ
PZH
PHL

VCC/2

t

h

VCC/2VCC/2

VCC/2 VCC/2

are the same as t
are the same as ten.

are the same as tpd.

dis

.

t

PHL

V

0 V

V

0 V

V

0 V

V

V

CC

CC

CC

OH

OL

Input

Output

Control

(low-level

enabling)

Output

Waveform 1

S1 at 2 × V

(see Note B)

Output

Waveform 2

S1 at Open

(see Note B)

VOLTAGE WAVEFORMS

PULSE DURATION

t

PZL

CC

t

PZH

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

VCC/2

VCC/2

t

w

V

0 V

V

0 V

V

V

V

0 V

CC

CC

CC

OL

OH

VCC/2VCC/2

VCC/2VCC/2

t

PLZ

VOL + 0.15 V

t

PHZ

VOH – 0.15 V

Figure 1. Load Circuit and Voltage Waveforms

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5

SN74ALVCH245
OCTAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS

SCES119D – JULY 1997 – REVISED MAY 1999

PARAMETER MEASUREMENT INFORMATION

From Output

Under Test

CL = 30 pF

(see Note A)

500 Ω

500 Ω

S1

V

= 2.5 V ± 0.2 V

CC

2 × V

CC

Open

GND

TEST S1

t

pd

t

PLZ/tPZL

t

PHZ/tPZH

Open

2 × V

GND

CC

LOAD CIRCUIT

Timing

Input

t

Data

Input

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

Input

t

PLH

Output

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. t

F. t

G. t

VCC/2 VCC/2

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

and t

PLZ
PZL
PLH

and t

and t

PHZ
PZH

PHL

VCC/2

t

su

are the same as t
are the same as ten.
are the same as tpd.

h

VCC/2VCC/2

VCC/2 VCC/2

.

dis

t

PHL

V

0 V

V

0 V

V

0 V

V

V

CC

CC

CC

OH

OL

Input

Output

Control

(low-level

enabling)

Output

Waveform 1

S1 at 2 × V

(see Note B)

Output

Waveform 2

S1 at GND

(see Note B)

VOLTAGE WAVEFORMS

PULSE DURATION

t

PZL

CC

t

PZH

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

VCC/2

VCC/2

t

w

V

0 V

V

0 V

V

V

V

0 V

CC

CC

CC

OL

OH

VCC/2VCC/2

VCC/2VCC/2

t

PLZ

VOL + 0.15 V

t

PHZ

VOH – 0.15 V

Figure 2. Load Circuit and Voltage Waveforms

6

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SN74ALVCH245

OCTAL BUS TRANSCEIVER

WITH 3-STATE OUTPUTS

SCES119D – JULY 1997 – REVISED MAY 1999

PARAMETER MEASUREMENT INFORMATION

= 2.7 V AND 3.3 V ± 0.3 V

V

CC

From Output

Under Test

CL = 50 pF

(see Note A)

Timing

Input

Data

Input

Input

t

PLH

Output

500 Ω

500 Ω

LOAD CIRCUIT

1.5 V

t

su

1.5 V 1.5 V

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

1.5 V 1.5 V

1.5 V 1.5 V

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

t

h

S1

t

PHL

6 V

GND

2.7 V

0 V

2.7 V

0 V

2.7 V

0 V

V

V

Open

OH

OL

Input

Output

Control

(low-level

enabling)

Output

Waveform 1

S1 at 6 V

(see Note B)

Output

Waveform 2

S1 at GND

(see Note B)

TEST S1

t

pd

t

PLZ/tPZL

t

PHZ/tPZH

1.5 V 1.5 V

VOLTAGE WAVEFORMS

PULSE DURATION

t

PZL

t

PZH

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

t

w

1.5 V

1.5 V

Open

6 V

GND

1.5 V1.5 V

t

PLZ

VOL + 0.3 V

t

PHZ

VOH – 0.3 V

2.7 V

0 V

2.7 V

0 V

3 V

V

OL

V

OH

0 V

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR≤10 MHz, ZO = 50 Ω, tr ≤2.5 ns, tf ≤2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. t

F. t

G. t

PLZ
PZL
PLH

and t
and t

and t

are the same as t

PHZ

are the same as ten.

PZH

are the same as tpd.

PHL

dis

.

Figure 3. Load Circuit and Voltage Waveforms

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7

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Copyright  1999, Texas Instruments Incorporated