Page 1
SN74ALVCH16901
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH PARITY GENERATORS/CHECKERS
SCES010E – JULY 1995 – REVISED FEBRUARY 1999
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Member of the Texas Instruments
Widebus+
Family
D
EPIC
(Enhanced-Performance Implanted
CMOS) Submicron Process
D
UBT
(Universal Bus Transceiver)
Combines D-Type Latches and D-Type
Flip-Flops for Operation in Transparent,
Latched, or Clocked Mode
D
Simultaneously Generates and Checks
Parity
D
Option to Select Generate Parity and Check
or Feed-Through Data/Parity in A-to-B or
B-to-A Directions
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D
Latch-Up Performance Exceeds 250 mA Per
JESD 17
D
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D
Packaged in Thin Shrink Small-Outline
Package
description
This 18-bit (dual-octal) noninverting registered
transceiver is designed for 1.65-V to 3.6-V V
CC
operation.
The SN74AL VCH16901 is a dual 9-bit to dual 9-bit
parity transceiver with registers. The device can
operate as a feed-through transceiver or it can
generate/check parity from the two 8-bit data
buses in either direction.
The SN74ALVCH16901 features independent clock (CLKAB or CLKBA), latch-enable (LEAB or LEBA), and
dual 9-bit clock-enable (CLKENAB
or CLKENBA) inputs. It also provides parity-enable (SEL) and parity-select
(ODD/EVEN
) inputs and separate error-signal (ERRA or ERRB) outputs for checking parity. The direction of
data flow is controlled by OEAB
and OEBA. When SEL is low, the parity functions are enabled. When SEL is
high, the parity functions are disabled and the device acts as an 18-bit registered transceiver.
T o ensure the high-impedance state during power up or power down, OE
should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74ALVCH16901 is characterized for operation from –40°C to 85°C.
Copyright 1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
DGG PACKAGE
(TOP VIEW)
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1CLKENAB
LEAB
CLKAB
1ERRA
1APAR
GND
1A1
1A2
1A3
V
CC
1A4
1A5
1A6
GND
1A7
1A8
2A1
2A2
GND
2A3
2A4
2A5
V
CC
2A6
2A7
2A8
GND
2APAR
2ERRA
OEAB
SEL
2CLKENAB
1CLKENBA
LEBA
CLKBA
1ERRB
1BPAR
GND
1B1
1B2
1B3
V
CC
1B4
1B5
1B6
GND
1B7
1B8
2B1
2B2
GND
2B3
2B4
2B5
V
CC
2B6
2B7
2B8
GND
2BPAR
2ERRB
OEBA
ODD/EVEN
2CLKENBA
Widebus+, EPIC, and UBT are trademarks of Texas Instruments Incorporated.
Page 2
SN74ALVCH16901
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH PARITY GENERATORS/CHECKERS
SCES010E – JULY 1995 – REVISED FEBRUARY 1999
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Function Tables
FUNCTION
†
INPUTS
OUTPUT
CLKENAB OEAB LEAB CLKAB A
B
X H X X X Z
X LH XL L
X LH XH H
H LL XXB
0
‡
L LL ↑LL
L LL ↑HH
L LL LXB
0
‡
L LL HXB
0
§
†
A-to-B data flow is shown: B-to-A flow is similar, but uses OEBA,
LEBA, and CLKENBA
.
‡
Output level before the indicated steady-state input conditions were
established
§
Output level before the indicated steady-state input conditions were
established, provided that CLKAB was low before LEAB went low
PARITY ENABLE
INPUTS
SEL OEBA OEAB
OPERATION OR FUNCTION
L H L Parity is checked on port A and is generated on port B.
L L H Parity is checked on port B and is generated on port A.
L H H Parity is checked on port B and port A.
L L L Parity is generated on port A and B if device is in FF mode.
H L L QA data to B, QB data to A
H LH
Parity functions are disabled;
QB data to A
H HL
device
acts
as
a
standard
18-bit registered transceiver.
QA data to B
H H H
18 bit registered transceiver.
Isolation
Page 3
SN74ALVCH16901
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH PARITY GENERATORS/CHECKERS
SCES010E – JULY 1995 – REVISED FEBRUARY 1999
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Function Tables (Continued)
PARITY
INPUTS
OUTPUTS
SEL OEBA OEAB ODD/EVEN
Σ OF INPUTS
A1–A8 = H
Σ OF INPUTS
B1–B8 = H
APAR BPAR APAR
ERRA
BPAR
ERRB
L H L L 0, 2, 4, 6, 8 N/A L N/A N/A H L Z
L H L L 1, 3, 5, 7 N/A L N/A N/A LHZ
LH L L 0, 2, 4, 6, 8 N/A H N/A N/A LLZ
LH L L 1, 3, 5, 7 N/A H N/A N/A HHZ
LLH L N/A 0, 2, 4, 6, 8 N/A L L Z N/A H
L L H L N/A 1, 3, 5, 7 N/A L H Z N/A L
L L H L N/A 0, 2, 4, 6, 8 N/A H L Z N/A L
L L H L N/A 1, 3, 5, 7 N/A H H Z N/A H
L H L H 0, 2, 4, 6, 8 N/A L N/A N/A L H Z
L H L H 1, 3, 5, 7 N/A L N/A N/A HLZ
LH L H 0, 2, 4, 6, 8 N/A H N/A N/A HHZ
LH L H 1, 3, 5, 7 N/A H N/A N/A LLZ
LLH H N/A 0, 2, 4, 6, 8 N/A L H Z N/A L
L L H H N/A 1, 3, 5, 7 N/A L L Z N/A H
L L H H N/A 0, 2, 4, 6, 8 N/A H H Z N/A H
L L H H N/A 1, 3, 5, 7 N/A H L Z N/A L
L H H L 0, 2, 4, 6, 8 0, 2, 4, 6, 8 L L Z H Z H
L H H L 1, 3, 5, 7 1, 3, 5, 7 L L Z LZL
LH H L 0, 2, 4, 6, 8 0, 2, 4, 6, 8 H H Z LZL
LH H L 1, 3, 5, 7 1, 3, 5, 7 H H Z HZH
LHH H 0, 2, 4, 6, 8 0, 2, 4, 6, 8 L L Z L Z L
L H H H 1, 3, 5, 7 1, 3, 5, 7 L L Z HZH
LH H H 0, 2, 4, 6, 8 0, 2, 4, 6, 8 H H Z HZH
LH H H 1, 3, 5, 7 1, 3, 5, 7 H H Z LZL
LLL L N/A N/A N/A N/A PE
†
Z PE
†
Z
L L L H N/A N/A N/A N/A PO
‡
Z PO
‡
Z
†
Parity output is set to the level so that the specific bus side is set to even parity.
‡
Parity output is set to the level so that the specific bus side is set to odd parity.
Page 4
SN74ALVCH16901
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH PARITY GENERATORS/CHECKERS
SCES010E – JULY 1995 – REVISED FEBRUARY 1999
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional block diagram
A-Port
Parity
Generate
and
Check
B Data
B-Port
Parity
Generate
and
Check
A Data
18-Bit
Storage
18-Bit
Storage
18 18
1818
2
2
LEAB
1CLKENAB
2CLKENAB
CLKAB
OEAB
1A1–1A8
1APAR
1ERRB
2A1–2A8
2APAR
2ERRB
ODD/EVEN
SEL
OEBA
1B1–1B8
1BPAR
1ERRA
2B1–2B8
2BPAR
2ERRA
1CLKENBA
2CLKENBA
CLKBA
LEBA
Q
A
Q
B
5
61
28
36
34
31
35
60
4
37
29
62
64, 33
63
2
1, 32
3
30
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, V
CC
–0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
: Except I/O ports (see Note 1) –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O ports (see Notes 1 and 2 –0.5 V to V
CC
+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, V
O
(see Notes 1 and 2) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(VI < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O
±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through each V
CC
or GND ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
JA
(see Note 3) 73°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed..
2. This value is limited to 4.6 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51.
Page 5
SN74ALVCH16901
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH PARITY GENERATORS/CHECKERS
SCES010E – JULY 1995 – REVISED FEBRUARY 1999
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions (see Note 4)
MIN MAX UNIT
V
CC
Supply voltage 1.65 3.6 V
VCC = 1.65 V to 1.95 V 0.65 × V
CC
V
IH
High-level input voltage
VCC = 2.3 V to 2.7 V
1.7
V
VCC = 2.7 V to 3.6 V 2
VCC = 1.65 V to 1.95 V 0.35 × V
CC
V
IL
Low-level input voltage
VCC = 2.3 V to 2.7 V
0.7
V
VCC = 2.7 V to 3.6 V 0.8
V
I
Input voltage 0 V
CC
V
V
O
Output voltage 0 V
CC
V
VCC = 1.65 V –4
p
VCC = 2.3 V –12
IOHHigh-level output current
VCC = 2.7 V –12
mA
VCC = 3 V –24
VCC = 1.65 V 4
p
VCC = 2.3 V 12
IOLLow-level output current
VCC = 2.7 V 12
mA
VCC = 3 V 24
∆t/∆v Input transition rise or fall rate 10 ns/V
T
A
Operating free-air temperature –40 85 °C
NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs
, literature number SCBA004.
Page 6
SN74ALVCH16901
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH PARITY GENERATORS/CHECKERS
SCES010E – JULY 1995 – REVISED FEBRUARY 1999
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS
V
CC
MIN TYP†MAX UNIT
IOH = –100 µA 1.65 V to 3.6 V VCC–0.2
IOH = –4 mA 1.65 V 1.2
IOH = –6 mA 2.3 V 2
V
OH
2.3 V 1.7
V
IOH = –12 mA
2.7 V 2.2
3 V 2.4
IOH = –24 mA 3 V 2
IOL = 100 µA 1.65 V to 3.6 V 0.2
IOL = 4 mA 1.65 V 0.45
IOL = 6 mA 2.3 V 0.4
V
OL
2.3 V 0.7
V
I
OL
= 12
mA
2.7 V 0.4
IOL = 24 mA 3 V 0.55
I
I
VI = VCC or GND 3.6 V ±5 µA
VI = 0.58 V 1.65 V 25
VI = 1.07 V 1.65 V –25
VI = 0.7 V 2.3 V 45
I
I(hold)
VI = 1.7 V 2.3 V –45
µA
()
VI = 0.8 V 3 V 75
VI = 2 V 3 V –75
VI = 0 to 3.6 V
‡
3.6 V ±500
I
OZ
§
VO = VCC or GND 3.6 V ±10 µA
I
CC
VI = VCC or GND, IO = 0 3.6 V 40 µA
∆I
CC
One input at VCC – 0.6 V, Other inputs at VCC or GND 3 V to 3.6 V 750 µA
C
i
Control inputs VI = VCC or GND 3.3 V 3 pF
C
io
A or B ports VO = VCC or GND 3.3 V 7.5 pF
C
o
ERR ports VO = VCC or GND 3.3 V 6 pF
†
All typical values are at VCC = 3.3 V, TA = 25°C.
‡
This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.
§
For I/O ports, the parameter IOZ includes the input leakage current.
Page 7
SN74ALVCH16901
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH PARITY GENERATORS/CHECKERS
SCES010E – JULY 1995 – REVISED FEBRUARY 1999
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figures 1 through 3)
VCC = 1.8 V
VCC = 2.5 V
± 0.2 V
VCC = 2.7 V
VCC = 3.3 V
± 0.3 V
UNIT
MIN MAX MIN MAX MIN MAX MIN MAX
f
clock
Clock frequency
†
125 125 125 MHz
Pulse
CLK↑
†
3 3 3
t
w
duration
LE high
†
3 3 3
ns
A, APAR or B, BPAR before CLK↑
†
1.9 2 1.7
t
su
Setup time
CLKEN
before CLK↑
†
2.1 2.1 1.7
ns
A, APAR or B, BPAR before LE↓
†
1.4 1.3 1.2
A, APAR or B, BPAR after CLK↑
†
0.4 0.4 0.5
t
h
Hold time
CLKEN
after CLK↑
†
0.5 0.5 0.7
ns
A, APAR or B, BPAR after LE↓
†
0.9 1.1 0.9
†
This information was not available at the time of publication.
Page 8
SN74ALVCH16901
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH PARITY GENERATORS/CHECKERS
SCES010E – JULY 1995 – REVISED FEBRUARY 1999
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 1 through 3)
PARAMETER
FROM
TO
VCC = 1.8 V
VCC = 2.5 V
± 0.2 V
VCC = 2.7 V
VCC = 3.3 V
± 0.3 V
UNIT
(INPUT)
(OUTPUT)
MIN TYP MIN MAX MIN MAX MIN MAX
f
max
†
125 125 125 MHz
B or A
†
1 5.2 4.8 1 4.4
A or B
BPAR or APAR
†
2 8.9 7.6 2 6.7
BPAR or APAR
†
1 5.7 5.2 1 4.7
APAR or BPAR
ERRA or ERRB
†
2 9.7 8.7 2 7.5
ERRA or ERRB
†
1.5 8.7 7.9 1.5 6.8
ODD/EVEN
BPAR or APAR
†
1.5 8.3 7.6 1.5 6.5
SEL BPAR or APAR
†
1 6.1 5.9 1 5.1
A or B
†
1 6.4 5.8 1 5.1
t
pd
BPAR or APAR
parity feedthrough
†
1.5 7.1 6.3 1.5 5.6
ns
CLKAB or CLKBA
BPAR or APAR
parity generated
†
2.5 10.2 8.7 2 7.7
ERRA or ERRB
†
2.5 10.5 8.9 2 7.9
A or B
†
1 6 5.5 1 4.8
BPAR or APAR
parity feedthrough
†
1.5 6.7 6 1.5 5.3
LEAB or LEBA
BPAR or APAR
parity generated
†
2.5 9.8 8.3 2 7.4
ERRA or ERRB
†
2.5 9.9 8.5 2 7.5
t
en
OEAB or OEBA
B, BPAR or A,
APAR
†
1.4 6.3 6.1 1 5.3 ns
t
dis
OEAB or OEBA
B, BPAR or A,
APAR
†
1.3 6.1 5.2 1.5 4.9 ns
t
en
OEAB or OEBA
ERRA or ERRB
†
1.4 6.2 5.5 1 4.9 ns
t
dis
OEAB or OEBA
ERRA or ERRB
†
1.3 7.3 6.5 1 5.7 ns
t
en
SEL
ERRA or ERRB
†
1.4 6.7 6.5 1 5.5 ns
t
dis
SEL
ERRA or ERRB
†
1.3 6.4 5.4 1.5 4.9 ns
†
This information was not available at the time of publication.
operating characteristics, T
A
= 25°C
VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V
PARAMETER
TEST CONDITIONS
TYP TYP TYP
UNIT
Power dissipation
Outputs enabled
p
†
22 27
p
C
pd
capacitance
Outputs disabled
C
L
= 50 pF,f = 10 MHz
†
5 8
pF
†
This information was not available at the time of publication.
Page 9
SN74ALVCH16901
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH PARITY GENERATORS/CHECKERS
SCES010E – JULY 1995 – REVISED FEBRUARY 1999
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
V
CC
= 1.8 V
VCC/2
VCC/2
VCC/2VCC/2
VCC/2VCC/2
VCC/2
VCC/2
V
OH
V
OL
t
h
t
su
From Output
Under Test
CL = 30 pF
(see Note A)
LOAD CIRCUIT
S1
Open
GND
1 kΩ
1 kΩ
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2 × V
CC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
t
PZL
t
PZH
t
PLZ
t
PHZ
0 V
VOL + 0.15 V
VOH – 0.15 V
0 V
V
CC
0 V
0 V
t
w
V
CC
V
CC
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
Timing
Input
Data
Input
Input
t
pd
t
PLZ/tPZL
t
PHZ/tPZH
Open
2 × V
CC
GND
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. t
PLZ
and t
PHZ
are the same as t
dis
.
F. t
PZL
and t
PZH
are the same as ten.
G. t
PLH
and t
PHL
are the same as tpd.
0 V
V
CC
VCC/2
t
PHL
VCC/2 VCC/2
V
CC
0 V
V
OH
V
OL
Input
Output
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VCC/2 VCC/2
t
PLH
2 × V
CC
V
CC
Figure 1. Load Circuit and Voltage Waveforms
Page 10
SN74ALVCH16901
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH PARITY GENERATORS/CHECKERS
SCES010E – JULY 1995 – REVISED FEBRUARY 1999
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
V
CC
= 2.5 V ± 0.2 V
VCC/2
VCC/2
VCC/2VCC/2
VCC/2VCC/2
VCC/2
VCC/2
V
OH
V
OL
t
h
t
su
From Output
Under Test
CL = 30 pF
(see Note A)
LOAD CIRCUIT
S1
Open
GND
500 Ω
500 Ω
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2 × V
CC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
t
PZL
t
PZH
t
PLZ
t
PHZ
0 V
VOL + 0.15 V
VOH – 0.15 V
0 V
V
CC
0 V
0 V
t
w
V
CC
V
CC
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
Timing
Input
Data
Input
Input
t
pd
t
PLZ/tPZL
t
PHZ/tPZH
Open
2 × V
CC
GND
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. t
PLZ
and t
PHZ
are the same as t
dis
.
F. t
PZL
and t
PZH
are the same as ten.
G. t
PLH
and t
PHL
are the same as tpd.
0 V
V
CC
VCC/2
t
PHL
VCC/2 VCC/2
V
CC
0 V
V
OH
V
OL
Input
Output
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VCC/2 VCC/2
t
PLH
2 × V
CC
V
CC
Figure 2. Load Circuit and Voltage Waveforms
Page 11
SN74ALVCH16901
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH PARITY GENERATORS/CHECKERS
SCES010E – JULY 1995 – REVISED FEBRUARY 1999
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
V
CC
= 2.7 V AND 3.3 V ± 0.3 V
t
PLH
V
OH
V
OL
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1
6 V
Open
GND
500 Ω
500 Ω
t
PHL
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 6 V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
t
PZL
t
PZH
t
PLZ
t
PHZ
1.5 V1.5 V
1.5 V 1.5 V
2.7 V
0 V
1.5 V 1.5 V
V
OH
V
OL
0 V
1.5 V
VOL + 0.3 V
1.5 V
VOH – 0.3 V
0 V
1.5 V
2.7 V
0 V
0 V
2.7 V
0 V
Input
2.7 V
2.7 V
3 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
Timing
Input
Data
Input
Output
Input
t
pd
t
PLZ/tPZL
t
PHZ/tPZH
Open
6 V
GND
TEST S1
1.5 V 1.5 V
t
w
t
h
t
su
1.5 V 1.5 V
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. t
PLZ
and t
PHZ
are the same as t
dis
.
F. t
PZL
and t
PZH
are the same as ten.
G. t
PLH
and t
PHL
are the same as tpd.
Figure 3. Load Circuit and Voltage Waveforms
Page 12
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