Datasheet SN74ALVC7814-25DL, SN74ALVC7814-25DLR, SN74ALVC7814-40DL, SN74ALVC7814-40DLR Datasheet (Texas Instruments)

SN74ALVC7814

64 × 18

LOW-POWER FIRST-IN, FIRST-OUT MEMORY

SCAS592A – OCTOBER 1997 – REVISED APRIL 1998

D

Member of the Texas Instruments
Widebus Family

D

Low-Power Advanced CMOS Technology

D

Operates From 3-V to 3.6-V V

D

Load Clock and Unload Clock Can Be

CC

Asynchronous or Coincident

D

Full, Empty, and Half-Full Flags

D

Programmable Almost-Full/Almost-Empty
Flag

D

Fast Access Times of 18 ns With a 50-pF
Load and All Data Outputs Switching
Simultaneously

D

Data Rates up to 40 MHz

D

3-State Outputs

D

Pin-to-Pin Compatible With SN74ACT7804,
SN74ACT7806, and SN74ACT7814

D

Packaged in Shrink Small-Outline 300-mil
Package Using 25-mil Center-to-Center
Spacing

description

A FIFO memory is a storage device that allows
data to be written into and read from its array at
independent data rates. The SN74ALVC7814 is
an 18-bit FIFO with high speed and fast access
times. Data is processed at rates up to 40 MHz
with access times of 18 ns in a bit-parallel format.
These memories are designed for 3-V to 3.6-V
V

operation.

CC

Data is written into memory on a low-to-high
transition of the load clock (LDCK) and is read out
on a low-to-high transition of the unload clock
(UNCK). The memory is full when the number of
words clocked in exceeds the number of words
clocked out by 64. When the memory is full, LDCK
has no effect on the data residing in memory.
When the memory is empty , UNCK has no effect.

DL PACKAGE

(TOP VIEW)

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28

56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29

OE
Q17
Q16
Q15
GND
Q14
V
Q13
Q12
Q11
Q10
Q9
GND
Q8
Q7
Q6
Q5
V
Q4
Q3
Q2
GND
Q1
Q0
UNCK
NC
NC
EMPTY

RESET

D17
D16
D15
D14
D13
D12

D1 1

D10

V

CC

D9
D8

GND

D7
D6
D5
D4
D3
D2
D1
D0
HF

PEN

AF/AE

LDCK

NC
NC

FULL

NC – No internal connection

CC

CC

Status of the FIFO memory is monitored by the full (FULL
full/almost-empty (AF/AE) flags. The FULL
is not full. The EMPTY

output is low when the memory is empty and high when it is not empty . The HF output

output is low when the memory is full and high when the memory

), empty (EMPTY), half-full (HF), and almost-

is high whenever the FIFO contains 32 or more words and low when it contains 31 or fewer words. The AF/AE
status flag is a programmable flag. The first one or two low-to-high transitions of LDCK after reset are used to
program the almost-empty offset value (X) and the almost-full offset value (Y) if program enable (PEN
The AF/AE flag is high when the FIFO contains X or fewer words or (64 – Y) or more words. The AF/AE flag
is low when the FIFO contains between (X + 1) and (63 – Y) words.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Widebus is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  1998, Texas Instruments Incorporated

) is low.

1

SN74ALVC7814
64 × 18
LOW-POWER FIRST-IN, FIRST-OUT MEMORY

SCAS592A – OCTOBER 1997 – REVISED APRIL 1998

description (continued)

A low level on the reset (RESET) resets the internal stack pointers and sets FULL high, AF/AE high, HF low,
and EMPTY
The first word loaded into empty memory causes EMPTY
The data outputs are in the high-impedance state when the output-enable (OE

The SN74ALVC7814 is characterized for operation from 0°C to 70°C.

low. The Q outputs are not reset to any specific logic level. The FIFO must be reset on power up.

to go high and the data to appear on the Q outputs.

) is high.

logic symbol

†

Φ

FIFO 64 × 18

RESET

LDCK

UNCK

OE

PEN

D0
D1
D2
D3
D4
D5
D6
D7
D8

D9
D10
D11
D12
D13
D14
D15
D16

D17

1
25

32
56

23

21
20
19
18
17
16
15
14
12

11
9
8
7
6
5
4
3

2

RESET

LDCK
UNCK

EN1
Program Enable

0

Data

17

Full

Half-Full

Almost Full/Empty

Empty

Data

1

17

28

FULL

22

HF

24

AF/AE

29

EMPTY

33

0

34
36
37
38
40
41
42
43

45
46
47
48
49
51
53
54

55

Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8

Q9
Q10
Q11
Q12
Q13
Q14
Q15
Q16

Q17

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

2

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I/O

DESCRIPTION

functional block diagram

OE

D0–D17

UNCK

Read

Pointer

SN74ALVC7814

64 × 18

LOW-POWER FIRST-IN, FIRST-OUT MEMORY

SCAS592A – OCTOBER 1997 – REVISED APRIL 1998

RAM

64 × 18

LDCK

RESET

PEN

Write

Pointer

Reset
Logic

Status-

Flag

Logic

Q0–Q17

EMPTY
FULL

HF
AF/AE

Terminal Functions

TERMINAL

NAME NO.

Almost full/almost empty flag. Depth-offset values can be programmed for this flag or the default value

AF/AE 24 O

D0–D17
EMPTY 29 O Empty flag. EMPTY is low when the FIFO is empty. A FIFO reset also causes EMPTY to go low.

FULL 28 O Full flag. FULL is low when the FIFO is full. A FIFO reset causes FULL to go high.
HF 22 O Half-full flag. HF is high when the FIFO memory contains 32 or more words. HF is low after reset.
LDCK 25 I Load clock. Data is written to the FIFO on the rising edge of LDCK when FULL is high.
OE 56 I Output enable. When OE is high, the data outputs are in the high-impedance state.

PEN

Q0–Q17

RESET 1 I Reset. A low level on RESET resets the FIFO and drives AF/AE and FULL high and HF and EMPTY low.
UNCK 32 I Unload clock. Data is read from the FIFO on the rising edge of UNCK when EMPTY is high.

2–9, 11–12,

14–21

23 I

33–34, 36–38,
40–43, 45–49,

51, 53–55

of 64 can be used for both the almost empty offset (X) and the almost full offset (Y). AF/AE is high when
memory contains X or fewer words or (64 – Y) or more words. AF/AE is high after reset.

I 18-bit data input port

Program enable. After reset and before the first word is written to the FIFO, the binary value on D0–D7
is latched as an AF/AE offset value when PEN

O 18-bit data output port

is low and WRTCLK is high.

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3

4

ÎÎ

ÎÎ

ÎÎ

ÎÎ

ÎÎ

ÎÎ

ÎÎ

ÎÎ

ÎÎ

ÎÎ

ÎÎ

ÎÎ

ÎÎ

ÎÎ

ÎÎ

ÎÎ

ÎÎ

ÎÎ

ÎÎ

ÎÎ

ÎÎ

ÎÎ

ÎÎ

ÎÎ

ÎÎ

ÎÎ

ÎÎ

ÎÎ

ÎÎ

ÎÎ

ÎÎ

ÎÎ

ÎÎ

SCAS592A – OCTOBER 1997 – REVISED APRIL 1998

LOW-POWER FIRST-IN, FIRST-OUT MEMORY

SN74ALVC7814

64 × 18

RESET

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PEN

LDCK

D0–D17

UNCK

OE

Q0–Q17

EMPTY

AF/AE

W1 W2

(X+1)

1
0

W

A

B

C

Don’t Care

1
0

W

W1

W

W2 DE

(Y+1)

(Y+2)

G F

H I

HF

FULL

Define the AF/AE Flag Using the Default Value of X and Y

Figure 1. Write, Read, and Flag Timing Reference

DEVICE

SN74ALVC7814

LOW-POWER FIRST-IN, FIRST-OUT MEMORY

SCAS592A – OCTOBER 1997 – REVISED APRIL 1998

DATA-WORD NUMBERS FOR FLAG TRANSITIONS

TRANSITION WORD

A B C D E F G H I

SN74ALVC7814 W32 W(64 – Y) W64 W33 W34 W(64 – X) W(65 – X) W64 W64

Figure 1. Write, Read, and Flag Timing Reference (Continued)

offset values for AF/AE

The AF/AE flag has two programmable limits: the almost-empty offset value (X) and the almost-full offset
value (Y). They can be programmed after the FIFO is reset and before the first word is written to memory. The
AF/AE flag is high when the FIFO contains X or fewer words or (512 – Y) or more words.

64 × 18

To program the offset values, PEN

can be brought low after reset. On the following low-to-high transition of
LDCK, the binary value on D0–D7 is stored as the almost-empty offset value (X) and the almost-full offset
value (Y). Holding PEN

low for another low-to-high transition of LDCK reprograms Y to the binary value on
D0–D7 at the time of the second LDCK low-to-high transition. Writes to the FIFO memory are disabled while
the offsets are programmed. A maximum value of 32 can be programmed for either X or Y (see Figure 2). To
use the default values of X = Y = 8, PEN

RESET

LDCK

PEN

D0–D17

EMPTY

Don’t Care

must be held high.Figure 1

Don’t Care

X and Y Y

Figure 2. Programming X and Y Separately

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5

SN74ALVC7814

UNIT

VOHFlags, Q outputs

V

64 × 18
LOW-POWER FIRST-IN, FIRST-OUT MEMORY

SCAS592A – OCTOBER 1997 – REVISED APRIL 1998

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V
Input voltage range, V
Output voltage range, V
Input clamp current, I
Output clamp current, I
Continuous output current, I
Continuous current through V

Voltage applied to a disabled 3-state output –0.5 V to 3.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Package thermal impedance, θ
Storage temperature range, T

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output voltage ratings can be exceeded if the input and output clamp-current ratings are observed.

2. This value is limited to 4.6 V maximum.

3. The package thermal impedance is calculated in accordance with JESD 51.

–0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC

(see Note 1) –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I

(see Notes 1 and 2) –0.5 V to V

O

(V

< 0)

IK

I

(V

OK

< 0 or V

O

(V

O

O

or GND ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC

(see Note 3) 74°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

JA

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

> VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

O

= 0 to VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC

*

+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

recommended operating conditions

’ALVC7814-25 ’ALVC7814-40

MIN MAX MIN MAX

V
V
V
V
V
I
I
T

OH
OL

Supply voltage 3 3.6 3 3.6 V

CC

High-level input voltage 2 2 V

IH

Low-level input voltage 0.8 0.8 V

IL

Input voltage 0 V

I

Output voltage 0 V

O

High-level output current, Q outputs, flags VCC = 3 V –8 –8 mA
Low-level output current, Q outputs, flags VCC = 3 V 16 16 mA
Operating free-air temperature 0 70 0 70 °C

A

CC
CC

0 V
0 V

CC
CC

V
V

†

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP‡MAX UNIT

VCC = 3 V to 3.6 V, IOH = –100 µA VCC–0.2

p

VCC = 3 V, IOH = –8 mA 2.4

Flags, Q outputs VCC = 3 V to 3.6 V, IOL = 100 µA 0.2

V

I

I

I

OZ

I

CC

∆I
C
C

‡

All typical values are at VCC = 3.3 V, TA = 25°C.

§

This is the supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC.

Flags VCC = 3 V, IOL = 8 mA 0.4

OL

Q outputs VCC = 3 V, IOL = 16 mA 0.55

VCC = 3.6 V, VI =VCC or GND ±5 µA
VCC = 3.6 V, VO =VCC or GND ±10 µA
VCC = 3.6 V, VI = VCC or GND, IO = 0 40 µA

CC
i
o

§

VCC = 3.6 V, One input at VCC–0.6 V, Other inputs at VCC or GND 500 µA
VCC = 3.3 V, VI = VCC or GND 3 pF
VCC = 3.3 V, VO = VCC or GND 6 pF

V

6

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UNIT

thHold time

ns

PARAMETER

UNIT

t

Any Q

ns

t

EMPTY

ns

t

FULL

ns

t

AF/AE

ns

t

ns

t

HF

ns

SN74ALVC7814

LOW-POWER FIRST-IN, FIRST-OUT MEMORY

SCAS592A – OCTOBER 1997 – REVISED APRIL 1998

timing requirements over recommended operating conditions (see Figures 1 through 3)

’ALVC7814-25 ’ALVC7814-40

MIN MAX MIN MAX

f

clock

t

w

t

su

Clock frequency 40 25 MHz

D0–D17 high or low 8 12
LDCK high or low 8 12

Pulse duration

Setup time

UNCK high or low
PEN low 8 12
RESET low 10 12
D0–D17 before LDCK↑ 5 5
LDCK inactive before RESET
PEN before LDCK↑ 8 8
D0–D17 after LDCK↑ 0 0
PEN high after LDCK low 0 0
PEN low after LDCK↑ 3 3
LDCK inactive after RESET high 6 6

high 6 6

8 12

64 × 18

ns

ns

switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C

f

max

pd

t

PLH

PHL

PLH

t

PHL

pd

PLH

PHL

t

en

t

dis

= 50 pF (unless otherwise noted) (see Figure 3)

L

FROM TO

(INPUT) (OUTPUT)

LDCK or UNCK 40 25 MHz

LDCK↑

UNCK↑

LDCK↑

UNCK↑

RESET low

UNCK↑

RESET low

LDCK↑
LDCK↑

UNCK↑

RESET low AF/AE 2 12 2 14

LDCK↑ HF 5 20 5 22

UNCK↑

RESET low

OE
OE

EMPTY

FULL

Any Q 2 10 2 11 ns
Any Q 2 11 2 12 ns

’ALVC7814-25 ’ALVC7814-40

MIN MAX MIN MAX

9 22 9 24
6 18 6 20
6 17 6 19 ns
6 17 6 19
4 18 4 20
6 17 6 19
4 20 4 22
6 17 6 19 ns
7 20 7 22
7 20 7 22

7 20 7 22
3 14 3 16

operating characteristics, VCC = 3.3 V, TA = 25°C

C

PARAMETER TEST CONDITIONS TYP UNIT

Power dissipation capacitance per FIFO channel Outputs enabled CL = 50 pF, f = 5 MHz 53 pF

pd

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

7

SN74ALVC7814
64 × 18
LOW-POWER FIRST-IN, FIRST-OUT MEMORY

SCAS592A – OCTOBER 1997 – REVISED APRIL 1998

PARAMETER MEASUREMENT INFORMATION

From Output

Under Test

CL = 50 pF

(see Note A)

LOAD CIRCUIT FOR OUTPUTS

Timing

Input

Data

Input

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

Input

(see Note C)

t

PLH

Output

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤2.5 ns, tf ≤2.5 ns.

1.5 V 1.5 V

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

500 Ω

500 Ω

1.5 V

t

su

1.5 V 1.5 V

1.5 V 1.5 V

t

h

S1

t

PHL

6 V

Open

GND

3 V

0 V

3 V

0 V

3 V

0 V

V

V

OH

OL

Input

Output

Control

(low-level

enabling)

Output

Waveform 1

S1 at 6 V

(see Note B)

Output

Waveform 2

S1 at GND

(see Note B)

PARAMETER S1

t

t

en

t

dis

t

pdtPLH/tPHL

1.5 V 1.5 V

VOLTAGE WAVEFORMS

t

PZL

t

PZH

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

PZH

t

PZL

t

PHZ
PLZ

t

w

PULSE DURATION

t

1.5 V

t

1.5 V

GND

6 V

GND

6 Vt

Open

1.5 V1.5 V

PLZ

VOL + 0.3 V

PHZ

VOH – 0.3 V

3 V

0 V

3 V

0 V

3 V

V

V

0 V

OL

OH

Figure 3. Standard CMOS Outputs (FULL, EMPTY, HF, AF/AE)

8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN74ALVC7814

64 × 18

LOW-POWER FIRST-IN, FIRST-OUT MEMORY

SCAS592A – OCTOBER 1997 – REVISED APRIL 1998

TYPICAL CHARACTERISTICS

SUPPLY CURRENT

vs

CLOCK FREQUENCY

140

f

= 1/2 f

data

TA = 75°C

120

CL = 0 pF

100

80

60

– Supply Current – mA

40

CC(f)

I

20

clock

VCC = 3.6 V

VCC = 3.3 V

VCC = 3 V

0

0 102030405060708090

f

– Clock Frequency – MHz

clock

Figure 4

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9

SN74ALVC7814
64 × 18
LOW-POWER FIRST-IN, FIRST-OUT MEMORY

SCAS592A – OCTOBER 1997 – REVISED APRIL 1998

APPLICATION INFORMATION

LDCK

FULL

D18–D35

D0–D17

SN74ALVC7814

UNCKLDCK

FULL

D0–D17 Q0–Q17

SN74ALVC7814

LDCK

FULL

D0–D17

EMPTY

OE OE

UNCK

EMPTY

OE

Q0–Q17

Figure 5. Word-Width Expansion: 64 36 Bits

UNCK

EMPTY

Q18–Q35

Q0–Q17

10

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